Fix RV32IM bitwise M31 word collisions

[this-vishalsingh]

Summary

• bind RV32IM AND/OR/XOR and ANDI/ORI/XORI bit witnesses to low/high 16-bit limbs instead of reconstructing full 32-bit words in M31
• emit individual bit, limb, and logic constraints from evaluate_all instead of one cancelable aggregate per bitwise instruction
• derive STARK constraint alpha count from the actual AIR constraint vector so the expanded constraints are included
• update bitwise benchmarks for vector-valued bitwise constraints

Closes #11.

Review notes

PR #12 is not sufficient: it avoids the collision by ignoring bit 31, which rejects valid RV32 values such as 0x80000000 ^ 0 = 0x80000000. This PR preserves full RV32 semantics.

Verification

• cargo test -p zp1-air
• cargo test -p zp1-air --benches
• cargo check --workspace
• cargo check -p zp1-prover
• cargo bench -p zp1-air --bench constraint_bench Bitwise_Constraints