The-RTL-Files

A collection of verilog designs, ranging from adders to MUX's & DeMUX's.

Name		Name	Last commit message	Last commit date
Latest commit History 92 Commits
1 to 8 Demultiplexer		1 to 8 Demultiplexer
2 to 1 MUX - Conditional Operator		2 to 1 MUX - Conditional Operator
2 to 4 Decoder		2 to 4 Decoder
2-Bit Magnitude Comparator		2-Bit Magnitude Comparator
3 to 8 Decoder		3 to 8 Decoder
32 bit Floating Point Multiplier		32 bit Floating Point Multiplier
4 Bit Parallel Subtractor		4 Bit Parallel Subtractor
4 Bit Ripple Carry Adder		4 Bit Ripple Carry Adder
4 Bit SIPO Shift Register		4 Bit SIPO Shift Register
4 to 2 Priority Encoder		4 to 2 Priority Encoder
8 to 3 Priority Encoder with Valid bit		8 to 3 Priority Encoder with Valid bit
BCD Adder		BCD Adder
Binary Multiplier		Binary Multiplier
Binary to Excess 3 Code Converter		Binary to Excess 3 Code Converter
D Latch		D Latch
Full Adder		Full Adder
README.md		README.md

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