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[XPU] Bump vllm_xpu_kernels to v0.1.11.1#11

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[XPU] Bump vllm_xpu_kernels to v0.1.11.1#11
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Summary

Bumps the pinned vllm_xpu_kernels release from v0.1.11 to v0.1.11.1 in requirements/xpu.txt. This is a real, currently-affecting-every-MoE-forward-pass-on-XPU bug fix, not a routine version bump.

Why this isn't a duplicate

Searched gh pr list --search "vllm_xpu_kernels" (open) — no existing PR bumps to this specific release. The precedent bump PR (vllm-project/vllm#46607, v0.1.10.1) is merged and unrelated to this fix.

Root cause

Upstream commit f7aadae5e5 ("add pad-aware reduce path", merged 2026-07-14) added two optional args (topk_ids, expert_map) to the moe_sum custom op — but only updated the CUDA-side registration and kernel. The XPU-side vllm_xpu_kernels package (pinned at v0.1.11) still only registers the old 2-arg schema:

RuntimeError: _moe_C::moe_sum() expected at most 2 argument(s) but received 4 argument(s).
Declaration: _moe_C::moe_sum(Tensor input, Tensor($0! -> ) output) -> ()

Every Python call site (vllm/model_executor/layers/fused_moe/fused_moe.py) passes all 4 positional args regardless of platform, so every MoE forward pass on XPU with fresh main currently crashes — this affects any XPU user running an MoE model, not a narrow edge case. I hit this while testing afierka-intel/vllm#6 (VLLMZ-1811).

v0.1.11.1 cherry-picks the fix: vllm-project/vllm-xpu-kernels#462 ("moe_sum interface align with cuda"), which adds the matching 4-arg XPU registration/kernel and negative-path validation tests.

Test plan

Verified on real Intel Arc Pro B70 hardware (not just reading the diff):

  1. Reproduced the crash against the currently-pinned v0.1.11 wheel: torch.ops._moe_C.moe_sum(input, output, None, None) → the exact RuntimeError above.
  2. Applied the v0.1.11.1 wheel (overlaid _moe_C.abi3.so + Python files into site-packages/vllm_xpu_kernels/, since pip install on the downloaded .whl file hit an unrelated pip CLI parsing bug with the 4-segment version string — worked around by extracting the wheel as a zip and copying files directly, which is functionally equivalent to what pip install would do).
  3. Confirmed the fix: the same 4-arg call now succeeds.
  4. Numerically verified correctness, not just "doesn't crash": compared moe_sum output against a plain torch.sum(dim=1) reference on random input — bit-exact match (max diff: 0.0).

AI assistance was used (Claude Code) for investigation and verification; I reviewed the change and ran the tests above personally on B70 hardware.

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zhenwei-intel and others added 2 commits July 17, 2026 10:54
Signed-off-by: zhenwei-intel <zhenwei.liu@intel.com>
v0.1.11.1 cherry-picks vllm-project/vllm-xpu-kernels#462, which fixes a
real XPU/CUDA op-signature mismatch: an unrelated commit (f7aadae,
"add pad-aware reduce path") added two optional args (topk_ids,
expert_map) to the moe_sum custom op on the CUDA side, but
vllm_xpu_kernels v0.1.11 (the currently pinned release) never registered
the matching 4-arg XPU schema. Every call site in
vllm/model_executor/layers/fused_moe/fused_moe.py passes all 4
positional args regardless of platform, so this crashes on XPU:

  RuntimeError: _moe_C::moe_sum() expected at most 2 argument(s) but
  received 4 argument(s). Declaration: _moe_C::moe_sum(Tensor input,
  Tensor($0! -> ) output) -> ()

This affects every MoE forward pass on XPU with fresh main, not a
narrow edge case.

Verified on real B70 (Intel Arc Pro) hardware: reproduced the crash
against the currently-pinned v0.1.11 wheel, then overlaid the v0.1.11.1
wheel's _moe_C.abi3.so and confirmed the 4-arg call now succeeds and
is bit-exact against a plain torch.sum(dim=1) reference (max diff:
0.0).

Co-authored-by: Claude <noreply@anthropic.com>
Signed-off-by: Artur Fierka <artur.fierka@intel.com>
@afierka-intel
afierka-intel force-pushed the afierka/bump-vllm-xpu-kernels-0.1.11.1 branch from bc0df7b to 9bee2e5 Compare July 17, 2026 11:06
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