[Kernel] TD scatter path for MoE write_zeros_to_output#5
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Adds a tensor-descriptor (TD) A gather + B load path to fused_moe_kernel_gptq_awq for int4_w4a16 (GPTQ/AWQ, packed 2 nibbles/byte along K), closing the last MoE Triton kernel without any TD coverage. This is infrastructure-completion work for RFC vllm-project#42545's adoption goal, not a proven optimization -- kernel-level benchmarks below show a mixed perf picture, not a clear win. B's packed layout is handled by building the descriptor at half-K-width (byte granularity) and using tl.interleave to reconstruct the full-K tile from the unpacked nibbles, matching the existing pointer path's even-k/low-nibble, odd-k/high-nibble convention. Verified bit-exact against the pointer path on B70, including the K-tail (block_k_diviable=False) case that exercises the descriptor's automatic zero-fill. int8_w8a16 has no TD path in this kernel: a Triton-XPU 3.7.1 codegen bug corrupts output whenever a descriptor-loaded uint8 B tile is multiplied by a dequant scale and fed into tl.dot, at exactly the BLOCK_SIZE_N=64 config this kernel's wna16 launcher uses by default for int8. Root-caused via isolated micro-probes (tile-shape sweep: fails whenever BLOCK_SIZE_N>=64 and BLOCK_SIZE_M!=32; ruled out the bf16-cast workaround that fixed a similar unified-attention bug, multiply-before- transpose, and splitting the dot width -- none fixed it) to a genuine compiler issue, not this kernel's logic. resolve_moe_gptq_awq_use_td() never returns True for int8 regardless of the env var, and a dedicated regression test pins this so a future accidental re-enable is caught loudly instead of silently corrupting output. The upstream bug report is a follow-up, not blocking this change. TD is XPU-only. On-device tl.make_tensor_descriptor(...).gather() (used for A) requires Blackwell (sm_100+) on CUDA and fails PTX codegen on older architectures -- verified empirically on H200 (Hopper, sm_90): `.gather()` hard-fails at ptxas regardless of whether triton.set_allocator is called first. resolve_moe_gptq_awq_use_td() now checks current_platform.is_xpu() before consulting the env var override, so VLLM_TRITON_USE_TD=1 can never route this kernel through device-side TD construction on non-XPU hardware. Gated on VLLM_TRITON_USE_TD (tri-state), independent of the shared registration in vllm-project#42436 / #5 / vllm-project#45781 -- whichever lands first keeps it, this one dedupes at rebase. Perf (kernel-level, isolating fused_moe_kernel_gptq_awq via the real fused_experts dispatch path, N=3 median per shape, Qwen1.5-MoE-A2.7B dims: hidden=2048, intermediate=1408, experts=60, topk=4): m=1 -0.4% (noise), m=16 +14.8%, m=64 -33.5%, m=256 -32.3%. TD trades a small decode-batch win for a real regression at moderate/large batch on this kernel; it is not a net perf improvement. E2E gsm8k on Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4 (20 real prompts, greedy decode): 20/20 exact-match generations TD-off vs TD-on, +1.7% median throughput in a hand-rolled offline-generate harness (not vllm bench) -- consistent with the kernel-level mixed picture given the model's batch-size mix. Correctness is unaffected either way; this is reported for reviewers to judge the tradeoff, not as a justification to default this on. Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Addresses code-review findings on #5: - Fix a missed third caller of write_zeros_to_output: fused_moe_nvfp4_emulation_kernel (experts/nvfp4_emulation_moe.py) still called the pre-TD 10-arg signature, missing the new num_valid_tokens positional. Because off_experts == -1 is a runtime branch (not constexpr), Triton compiles both branches on first launch, so any EP>1 run through the NVFP4-emulation fallback would hit "TypeError: missing 1 required positional argument: 'num_valid_tokens'" at compile time. Verified the crash reproduces against the pre-fix caller (isolated launcher, all-pruned expert_ids) on B200, and that the fix resolves it, both via a probe (this path has no existing unit test and isn't covered by writing one here). - Register the Triton scratch allocator before launching invoke_fused_moe_triton_kernel when the TD path is active. tl.make_tensor_descriptor builds the descriptor device-side, which requires a PyTorch-backed allocator registered via triton.set_allocator on CUDA -- without it, Triton raises "Kernel requires a runtime memory allocation, but no allocator was set" at runtime. The previous commit's "Verified on B200" claim was based on a standalone probe with its own allocator, not the integrated fused_moe_kernel; test_fused_moe_all_experts_pruned's TD cases in fact failed on B200 without this fix. Reuses the existing set_triton_allocator helper (vllm/triton_utils/allocation.py), following the same call-before-launch pattern used in fused_moe_lora_op.py (gated on its own use_tma flag) instead of init-time registration (used by olmo_gdn_linear_attn.py). - Add test_fused_moe_all_experts_pruned_int64_overflow: the existing test_fused_moe_int64_overflow only exercises the pointer path's offs_token.to(tl.int64) cast (no expert_map, so off_experts is never -1). Mirrors its M/N (row * N > int32 max) but also prunes every expert so every block hits the TD scatter path with scatter_idx landing near the overflow boundary. Verified with an isolated probe first that the tensor-descriptor's internal offset math does not overflow at this scale before writing the test. - Rename VLLM_TRITON_USE_TD -> VLLM_TRITON_MOE_WRITE_ZEROS_USE_TD. The old name suggested a general Triton-TD switch; it only gates this one zero-write helper. Also resolves the three-way env-var-name collision with vllm-project#42436 and vllm-project#45781 flagged in the previous commit. Re-verified end-to-end on all three platforms after these fixes: - XPU (B70): test_fused_moe_all_experts_pruned 4/4 pass (unchanged). - GPU (H200, Hopper): pointer-path cases pass, TD cases correctly skip (unchanged; TD remains unsupported on sm90). - GPU (B200, Blackwell): test_fused_moe_all_experts_pruned AND test_fused_moe_all_experts_pruned_int64_overflow both pass with use_td=True through the actual fused_moe_kernel (not a standalone probe) for the first time this session. Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Addresses code-review findings on #5: - Fix a missed third caller of write_zeros_to_output: fused_moe_nvfp4_emulation_kernel (experts/nvfp4_emulation_moe.py) still called the pre-TD 10-arg signature, missing the new num_valid_tokens positional. Because off_experts == -1 is a runtime branch (not constexpr), Triton compiles both branches on first launch, so any EP>1 run through the NVFP4-emulation fallback would hit "TypeError: missing 1 required positional argument: 'num_valid_tokens'" at compile time. Verified the crash reproduces against the pre-fix caller (isolated launcher, all-pruned expert_ids) on B200, and that the fix resolves it, both via a probe (this path has no existing unit test and isn't covered by writing one here). - Register the Triton scratch allocator before launching invoke_fused_moe_triton_kernel when the TD path is active. tl.make_tensor_descriptor builds the descriptor device-side, which requires a PyTorch-backed allocator registered via triton.set_allocator on CUDA -- without it, Triton raises "Kernel requires a runtime memory allocation, but no allocator was set" at runtime. The previous commit's "Verified on B200" claim was based on a standalone probe with its own allocator, not the integrated fused_moe_kernel; test_fused_moe_all_experts_pruned's TD cases in fact failed on B200 without this fix. Reuses the existing set_triton_allocator helper (vllm/triton_utils/allocation.py), following the same call-before-launch pattern used in fused_moe_lora_op.py (gated on its own use_tma flag) instead of init-time registration (used by olmo_gdn_linear_attn.py). - Add test_fused_moe_all_experts_pruned_int64_overflow: the existing test_fused_moe_int64_overflow only exercises the pointer path's offs_token.to(tl.int64) cast (no expert_map, so off_experts is never -1). Mirrors its M/N (row * N > int32 max) but also prunes every expert so every block hits the TD scatter path with scatter_idx landing near the overflow boundary. Verified with an isolated probe first that the tensor-descriptor's internal offset math does not overflow at this scale before writing the test. - Rename VLLM_TRITON_USE_TD -> VLLM_TRITON_MOE_WRITE_ZEROS_USE_TD. The old name suggested a general Triton-TD switch; it only gates this one zero-write helper. Also resolves the three-way env-var-name collision with vllm-project#42436 and vllm-project#45781 flagged in the previous commit. Re-verified end-to-end on all three platforms after these fixes: - XPU (B70): test_fused_moe_all_experts_pruned 4/4 pass (unchanged). - GPU (H200, Hopper): pointer-path cases pass, TD cases correctly skip (unchanged; TD remains unsupported on sm90). - GPU (B200, Blackwell): test_fused_moe_all_experts_pruned AND test_fused_moe_all_experts_pruned_int64_overflow both pass with use_td=True through the actual fused_moe_kernel (not a standalone probe) for the first time this session. Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Adds a tensor-descriptor (TD) A gather + B load path to fused_moe_kernel_gptq_awq for int4_w4a16 (GPTQ/AWQ, packed 2 nibbles/byte along K), closing the last MoE Triton kernel without any TD coverage. This is infrastructure-completion work for RFC vllm-project#42545's adoption goal, not a proven optimization -- kernel-level benchmarks below show a mixed perf picture, not a clear win. B's packed layout is handled by building the descriptor at half-K-width (byte granularity) and using tl.interleave to reconstruct the full-K tile from the unpacked nibbles, matching the existing pointer path's even-k/low-nibble, odd-k/high-nibble convention. Verified bit-exact against the pointer path on B70, including the K-tail (block_k_diviable=False) case that exercises the descriptor's automatic zero-fill. int8_w8a16 has no TD path in this kernel: a Triton-XPU 3.7.1 codegen bug corrupts output whenever a descriptor-loaded uint8 B tile is multiplied by a dequant scale and fed into tl.dot, at exactly the BLOCK_SIZE_N=64 config this kernel's wna16 launcher uses by default for int8. Root-caused via isolated micro-probes (tile-shape sweep: fails whenever BLOCK_SIZE_N>=64 and BLOCK_SIZE_M!=32; ruled out the bf16-cast workaround that fixed a similar unified-attention bug, multiply-before- transpose, and splitting the dot width -- none fixed it) to a genuine compiler issue, not this kernel's logic. resolve_moe_gptq_awq_use_td() never returns True for int8 regardless of the env var, and a dedicated regression test pins this so a future accidental re-enable is caught loudly instead of silently corrupting output. The upstream bug report is a follow-up, not blocking this change. TD is XPU-only. On-device tl.make_tensor_descriptor(...).gather() (used for A) requires Blackwell (sm_100+) on CUDA and fails PTX codegen on older architectures -- verified empirically on H200 (Hopper, sm_90): `.gather()` hard-fails at ptxas regardless of whether triton.set_allocator is called first. resolve_moe_gptq_awq_use_td() now checks current_platform.is_xpu() before consulting the env var override, so VLLM_TRITON_USE_TD=1 can never route this kernel through device-side TD construction on non-XPU hardware. Gated on VLLM_TRITON_USE_TD (tri-state), independent of the shared registration in vllm-project#42436 / #5 / vllm-project#45781 -- whichever lands first keeps it, this one dedupes at rebase. Perf (kernel-level, isolating fused_moe_kernel_gptq_awq via the real fused_experts dispatch path, N=3 median per shape, Qwen1.5-MoE-A2.7B dims: hidden=2048, intermediate=1408, experts=60, topk=4): m=1 -0.4% (noise), m=16 +14.8%, m=64 -33.5%, m=256 -32.3%. TD trades a small decode-batch win for a real regression at moderate/large batch on this kernel; it is not a net perf improvement. E2E gsm8k on Qwen1.5-MoE-A2.7B-Chat-GPTQ-Int4 (20 real prompts, greedy decode): 20/20 exact-match generations TD-off vs TD-on, +1.7% median throughput in a hand-rolled offline-generate harness (not vllm bench) -- consistent with the kernel-level mixed picture given the model's batch-size mix. Correctness is unaffected either way; this is reported for reviewers to judge the tradeoff, not as a justification to default this on. Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Artur Fierka <artur.fierka@intel.com>
Add a tensor-descriptor (TD) scatter path to write_zeros_to_output, the MoE zero-store helper for EP-pruned expert blocks (off_experts == -1). Store-side dual of the TD load pattern used elsewhere in the Triton MoE TD work -- uses tensor_descriptor.scatter() instead of pointer + mask. The descriptor's row-shape bound drops padded/out-of-rank token rows (the scatter API takes no mask). Gated on VLLM_TRITON_USE_TD (tri-state, shared with the existing unified-attention TD flag -- setting it affects both paths). Hardware support (moe_write_zeros_td_hw_supported()): XPU unconditionally (the Intel Triton backend lowers descriptor_scatter to a masked pointer store at the TTIR level for every XPU target, so there's no hardware feature gap to gate on); CUDA only sm100-family (tensor_descriptor.scatter lowers to PTX tile::scatter4, unsupported on Hopper and consumer Blackwell sm120/121). Forcing VLLM_TRITON_USE_TD=1 on unsupported hardware raises ValueError at call time. Defaults to off: a kernel-level microbenchmark (checked into benchmarks/kernels/benchmark_moe_write_zeros_td.py) shows the TD path slower than the pointer path at three of four measured problem sizes (+206%, +112%, +38%), converging to parity only at the largest. This is a store-side consistency change matching the existing TD load work, not a perf win, so it isn't auto-enabled by hardware capability alone. Quantized (gptq/awq) and NVFP4-emulation kernels stay on the pointer path. Tests: test_write_zeros_to_output_scatter_targets_correct_rows calls write_zeros_to_output directly with a pre-filled non-zero sentinel, so it can actually detect a wrong-row or no-op scatter -- unlike an end-to-end all-pruned assertion against fused_moe() output, which can't: fused_experts_impl pre-zeros intermediate_cache3 in Python whenever expert_map is not None, before either store path runs, so a broken scatter and a correct one produce identical all-zero output at that level. Kept the original all-pruned and mixed-EP end-to-end tests as coarser whole-pipeline sanity checks. Added test_fused_moe_all_experts_pruned_int64_overflow as a permanent regression test for the descriptor's int32 row-index cast. Co-authored-by: Claude <noreply@anthropic.com> Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Shorten comments and docstrings added for the TD scatter path: drop benchmark numbers (stale the moment they're re-measured, not load-bearing for understanding the code) and design-rationale prose that belongs in the PR description, not permanent source comments. No functional change. Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Consider to address the comments.
test_fused_moe_mixed_ep_td_matches_pointer asserted the pointer-path baseline output is non-zero before comparing against TD, but for small m the random top-k routing can select only pruned experts for every token, making that assertion fail on a legitimately all-zero baseline with no kernel defect. Reproduced on B70 hardware: m=1 failed ~1 in ~5 seeds. Bias one local expert's score so it's always selected. Signed-off-by: Artur Fierka <artur.fierka@intel.com>
Clarify DEVICE comment (ROCm also reports device_type "cuda"), replace illustrative PROBLEM_SIZES with real (m, n) pairs derived from Mixtral-8x7B and DeepSeek-V3 dims, and state in the module docstring why this script exists: AGENTS.md routes kernel perf work to benchmarks/kernels/, and it makes the TD-vs-pointer numbers backing resolve_moe_write_zeros_use_td()'s default-off gate independently reproducible. Signed-off-by: Artur Fierka <artur.fierka@intel.com>
The subagent-authored PROBLEM_SIZES rows had incorrect K values: Mixtral down-proj used K=4096 instead of intermediate_size=14336, and DeepSeek-V3 gate_up-proj used N=2048 (moe_intermediate_size itself) instead of N=2*moe_intermediate_size=4096, with a stale K=7168 (correct by coincidence for gate_up, but paired with the wrong N). Verified against E,N,_=w1.size(); K=w2.size(1) in fused_experts_impl and the w1=(e,2*n,k)/w2=(e,k,n) shape convention used throughout test_moe.py. Signed-off-by: Artur Fierka <artur.fierka@intel.com>
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Test PR — for review before submitting upstream
Test PR against my own fork's
main, opened for review before submitting tovllm-project/vllm. Not intended to merge here.Summary
write_zeros_to_output, the MoE zero-store helper for EP-pruned expert blocks (off_experts == -1).tensor_descriptor.scatter()instead of pointer + mask.USE_TDconstexpr /VLLM_TRITON_USE_TDenv var (tri-state: unset=auto,1/0=force). This flag is shared with the unified-attention TD path (triton_attn.py) — setting it affects both kernels, there's no independent control. Default (unset) is off for this path specifically: see Performance below.Hardware gating
tensor_descriptor.scatterlowers to PTXtile::scatter4(tcgen05/TMEM family) — no Hopper (sm90) equivalent, and unsupported on consumer Blackwell (sm120/121) per [NVIDIA] Enable TMA gather4 on sm_120 and sm_121 triton-lang/triton#8498. Gated onis_device_capability_family(100)(sm100 family, not blanket>=100).triton-intel-rewrite-tensor-descriptor-to-pointerpass unconditionally lowersdescriptor_scatterto a masked pointer store at the TTIR level for every XPU target (singletarget_arch, no per-generation dispatch as of the triton-xpu version this repo pins). Seemoe_write_zeros_td_hw_supported()docstring for the full argument and its limits.VLLM_TRITON_USE_TD=1on unsupported hardware now raisesValueErrorat call time (previously failed lazily at ptxas with an opaque compiler error) — verified on H200 (Hopper), see table below.Performance (kernel-level microbenchmark) — why this defaults to off
Standalone microbenchmark isolating
write_zeros_to_outputvia a thin launcher (no GEMM, nofused_moe()overhead), checked intobenchmarks/kernels/benchmark_moe_write_zeros_td.py(triton.testing.do_bench, median of 3 process-level repeats). Measures the store-path cost in isolation, not an E2E throughput claim.XPU (Battlemage B70). TD is slower than the pointer path at every measured size — only converging to parity (+1.1%) at the largest, most EP-realistic batch. This is a consistency change (store-side dual of the existing TD load work), not a perf win — the TD path defaults to off (
resolve_moe_write_zeros_use_td()returnsFalseunlessVLLM_TRITON_USE_TD=1is set explicitly), available for forced A/B testing but not auto-enabled by hardware capability. (The benchmark'sPROBLEM_SIZESwere subsequently updated to real Mixtral-8x7B / DeepSeek-V3 dims per review; the numbers above are from the original illustrative sizes and will be refreshed on the next run.)Correctness testing
The original all-pruned test (
test_fused_moe_all_experts_pruned, assertingfused_moe()output is all-zero) doesn't actually exercise the scatter:fused_experts_implpre-zerosintermediate_cache3in Python (intermediate_cache3.zero_()) wheneverexpert_map is not None, before either store path runs — so a correct scatter, a no-op, and a wrong-row scatter are all indistinguishable at that assertion. Addedtest_write_zeros_to_output_scatter_targets_correct_rows, which callswrite_zeros_to_outputdirectly through a thin launcher with a non-zero sentinel pre-filled before the kernel runs, and asserts both that valid rows are zeroed and that the out-of-bounds guard row is untouched. Includes a non-block-aligned N (104, not a multiple of BLOCK_SIZE_N=64) to cover the TD descriptor's column-bound clamp on a tail tile.Kept the original all-pruned and mixed-EP end-to-end tests as coarser whole-pipeline sanity checks, with docstrings noting they can't detect a scatter-targeting defect on their own.
Verified on real hardware (2026-07-17, this revision)
XPU (B70) and H200 (Hopper) were re-run against this revision's code, including the new sentinel-based scatter test. B200 (Blackwell sm100) could not be re-run this round — the B200 host was cluster-loaded (load avg >130, no card at genuine 0 MiB free) throughout the window; the prior-revision B200 rows are retained below and marked as such.
test_write_zeros_to_output_scatter_targets_correct_rows(6 cases)test_fused_moe_all_experts_pruned(4 cases)test_fused_moe_all_experts_pruned_int64_overflow(2 cases)resolve_moe_write_zeros_use_td()gatingFalse(default off); forced=1on XPU →True, no raisetest_write_zeros_to_output_scatter_targets_correct_rows(6 cases)use_td=False) + 3 skipped (use_td=True, correctly gated off sm90)test_fused_moe_mixed_ep_td_matches_pointer(2 cases)test_fused_moe_all_experts_pruned(4 cases)test_fused_moe_all_experts_pruned_int64_overflow(2 cases)VLLM_TRITON_USE_TD=1fail-fastValueErrorwith the expected message (unsupported-hardware guard works)Prior-revision runs (before this round's review fixes), retained for reference:
max diff = 0.0)test_fused_moe_all_experts_pruned(4 cases)fused_moe_kerneltest_fused_moe_all_experts_pruned_int64_overflow(2 cases)use_tdvaluesmax diff = 0.0)Still outstanding before upstream-ready:
test_write_zeros_to_output_scatter_targets_correct_rowsandtest_fused_moe_mixed_ep_td_matches_pointerhave not been run on B200 (sm100) in this test form — B200 is the only CUDA host where the TD scatter code path actually executes rather than skips, so the CUDA-side TD scatter is currently validated only by the prior-revision standalone cross-check, not the checked-in test. Needs a B200 pass when the cluster frees up.PROBLEM_SIZES(now real model dims) not yet re-run; Performance table above still reflects the original illustrative sizes.Test-harness notes found while running
test_fused_moe_mixed_ep_td_matches_pointer[1-1024-512]initially failed on B70 — but on its own precondition (count_nonzero(out_pointer) > 0), not the TD-vs-pointer comparison: withm=1, random top-k routing can select only pruned experts for the single token, yielding a legitimately all-zero pointer-path baseline. Fixed by biasing one local expert's score so it's always selected (commit "Fix flaky non-zero precondition in mixed-EP TD test"). Not a kernel defect.LD_LIBRARY_PATHomits/opt/intel/oneapi/umf/.../liband.../tcm/.../lib, which the Level-Zero loader needs — without themtorch.xpu.device_count()returns 0 despitezeInitsucceeding. Environment issue, not a code issue; flagged here for anyone reproducing on XPU.Test plan
test_write_zeros_to_output_scatter_targets_correct_rows(new): direct sentinel-based test of the scatter — 6/6 pass on B70; 3 pass + 3 correct-skip on H200 (see table). Not yet run on B200.test_fused_moe_all_experts_pruned(existing): coarse smoke test, all-pass on B70 / pass+skip on H200.test_fused_moe_all_experts_pruned_int64_overflow(existing): pass on B70 / pass+skip on H200.test_fused_moe_mixed_ep_td_matches_pointer(new checked-in test): skips on H200 (sm90). Not yet run on B200 in this form; prior-revision standalone cross-check was bit-identical on B70 + B200.ruff check+ruff format --check+ localpre-commitclean on all modified files.AI assistance was used (Claude Code) for implementation and testing. I reviewed every changed line; the 2026-07-17 XPU/H200 rows were run against this revision, the B200 rows are from a prior revision and B200 re-run on this revision is still pending.