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Auto PR: Differences detected #36

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74 changes: 73 additions & 1 deletion catalog/list.json
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Original file line number Diff line number Diff line change
@@ -1,6 +1,78 @@
{
"num": 87,
"num": 90,
"designs": [
{
"id": "-",
"title": "Agilex 7 FPGA - TinyML LiteRT Example Design Example on Nios® V/g Processor",
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@cohensus cohensus Jan 23, 2026

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Should be "System Example Design"

"source": "GitHub",
"family": "Agilex 7",
"quartus_version": "25.3.1",
"patch_number": "Unknown",
"devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
"device_part": "AGFB014R24B2E2V",
"description": "Nios® V/g Processor-based TinyML LiteRT example design on the Agilex® 7 FPGA.",
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Again should be "System Exmaple Design"

"rich_description": "<p>This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor in the Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/img/block_diagram.png\"/></p>",
"category": "AI",
"url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_niosv_g_tinyml_liteRT.zip",
"downloadUrl": "agilex7_niosv_g_tinyml_liteRT.zip",
"documentations": [
{
"title": "Design Document",
"downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_7_FPGA.md"
}
],
"Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344658973",
"Q_GITHUB_RELEASE": "25.3.1-v1.0",
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Why do we have v1.0 here? We are trying to have consistent naming convention. Can we have first version as 25.3.1 as release tag? If there are any more then you can add versions.

"Q_VALIDATED": true
},
{
"id": "-",
"title": "Agilex 7 FPGA - Nios V/m Transceiver Loopback design",
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Needs to be "Agilex 7 FPGA Nios V/m Transceiver Loopback System Example Design"

"source": "GitHub",
"family": "Agilex 7",
"quartus_version": "25.3.1",
"patch_number": "Unknown",
"devkit": "Agilex 7 FPGA F-Series Development Kit 2xF-Tile DK-DEV-AGF027F1ES",
"device_part": "AGFD023R24C2E1VC",
"description": "F-Tile Transceiver loopback design on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)",
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System Example Design

"rich_description": "<p>This design demonstrates the serial loopback via QSFPDD on Agilex™ 7 FPGA F-Series Development Kit (2xF-Tile)</p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/img/niosv_xcver.png\"/></p>",
"category": "Transceiver",
"url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_xcver_loopback.zip",
"downloadUrl": "agilex7_xcver_loopback.zip",
"documentations": [
{
"title": "Design Document",
"downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf027f1es-dev-devkit/niosv_m/xcver_ser_lp/docs/Nios_Vm_Processor_PAM4_8x53Gbps_with_QSFPDD_Serial_loopback_design.md"
}
],
"Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344685849",
"Q_GITHUB_RELEASE": "25.3.1-v1.0",
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25.3.1

"Q_VALIDATED": true
},
{
"id": "-",
"title": "Agilex 7 FPGA - Lockstep Example Design Example on Nios® V/g Processor",
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Should not be Example Design Example.....should be System Example Design

"source": "GitHub",
"family": "Agilex 7",
"quartus_version": "25.3.1",
"patch_number": "Unknown",
"devkit": "Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA",
"device_part": "AGFB014R24B2E2V",
"description": "Nios® V/g Processor-based Lockstep example design on the Agilex® 7 FPGA.",
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System Example Design

"rich_description": "<p>This design demonstrates the working of NiosV/g lockstep feature through the standard fail safe control mechanism using by injecting root faults and reading alarms with Nios® V/m as the system supervisor on Agilex® 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA. </p><p><img alt=\"image\" src=\"https://raw.githubusercontent.com/altera-fpga/agilex7f-nios-ed/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep/img/block_diagram.png\"/></p>",
"category": "Nios V",
"url": "https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1-v1.0/agilex7_niosv_g_lockstep.zip",
"downloadUrl": "agilex7_niosv_g_lockstep.zip",
"documentations": [
{
"title": "Design Document",
"downloadUrl": "https://github.com/altera-fpga/agilex7f-nios-ed/blob/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep/docs/Nios_Vg_Processor_Lockstep_Design_on_Agilex_7_FPGA.md"
}
],
"Q_DOWNLOAD_URL": "https://api.github.com/repos/altera-fpga/agilex7f-nios-ed/releases/assets/344655307",
"Q_GITHUB_RELEASE": "25.3.1-v1.0",
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Again, we need consistent naming convention

"Q_VALIDATED": true
},
{
"id": "-",
"title": "Agilex 7 FPGA - Lockstep Example Design Example on Nios V/g Processor",
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This says Example Design Example.....needs to be System Example Design

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