Support of wire declaration for the instance ports.

plugin/verilog_instance.py

@@ -8,8 +8,11 @@
 import sys
 
 skip_last_coma = 0
+wire_declaration = 0
 if len(sys.argv) > 1:
     skip_last_coma = int(sys.argv[1])
+    if len(sys.argv) > 2:
+        wire_declaration = int(sys.argv[2])
 
 keywords = []
 keywords.extend(["input", "output", "inout", "ref", "parameter", "localparam"])
@@ -31,6 +34,7 @@
 pattern_punctuation = re.compile(r'[,;]')
 pattern_two_words_no_coma = re.compile(r'^\s*(\w+)\s+(\w+.*)')
 pattern_spaces = re.compile(r'\s+')
+pattern_cpp_type_comment = re.compile(r'//.*')
 
 ports = []
 wait_to_close_comment = 0
@@ -53,26 +57,58 @@
         else:
             wait_to_close_comment = 1
             continue
-    # handle all other patterns
-    for pattern in patterns:
-        line = pattern.sub(' ', line)
-    # handle typedef, class and interfaces
-    line = pattern_two_words_no_coma.sub('\\2', line)
-    line = pattern_punctuation.sub(' ', line)
-    line = pattern_spaces.sub(' ', line)
-    # finally, get port names
-    line = line.strip()
-    if line != "":
-        ports.extend(line.split(' '))
-
-ports_nb = len(ports)
-i = 0
-if ports_nb > 0:
-    max_str_len = len(max(ports, key=len))
-    for port in ports:
-        skip_coma = skip_last_coma and i == (ports_nb - 1)
-        space_str = " " * (max_str_len - len(port))
-        indent_str = " " * indent_len
-        print("%s.%s%s (%s%s)%s" % (
-            indent_str, port, space_str, port, space_str, (",", "")[skip_coma]))
-        i = i + 1
+    if wire_declaration == 0:
+        # handle all other patterns
+        for pattern in patterns:
+            line = pattern.sub(' ', line)
+        # handle typedef, class and interfaces
+        line = pattern_two_words_no_coma.sub('\\2', line)
+        line = pattern_punctuation.sub(' ', line)
+        line = pattern_spaces.sub(' ', line)
+        # finally, get port names
+        line = line.strip()
+        if line != "":
+            ports.extend(line.split(' '))
+    else:
+        # print(line)
+        for a_line in line.splitlines():
+            # Remove cpp style comment (//)
+            a_line = pattern_cpp_type_comment.sub(' ', a_line)
+            # print(a_line)
+            # Remove trailing spaces
+            a_line = a_line.strip()
+            # if line connets is empty clear it
+            if a_line == "":
+                continue
+            # delete input or output
+            a_line = a_line.replace("input", " ")
+            a_line = a_line.replace("output", "")
+            # wire keyword
+            if "wire" not in a_line:
+                if "reg" in a_line:
+                    a_line = a_line.replace("reg", "wire")
+                else:
+                    a_line = "wire " + a_line
+
+            # semicolon
+            # print(a_line)
+            a_line = a_line.replace(",", ";")
+            a_line = a_line.strip()
+            # print(a_line)
+            if a_line[-1] != ';':
+                a_line = a_line + ';'
+            # print wire declaration
+            print (a_line)
+
+if wire_declaration == 0:
+    ports_nb = len(ports)
+    i = 0
+    if ports_nb > 0:
+        max_str_len = len(max(ports, key=len))
+        for port in ports:
+            skip_coma = skip_last_coma and i == (ports_nb - 1)
+            space_str = " " * (max_str_len - len(port))
+            indent_str = " " * indent_len
+            print("%s.%s%s (%s%s)%s" % (
+                indent_str, port, space_str, port, space_str, (",", "")[skip_coma]))
+            i = i + 1

plugin/verilog_instance.vim

@@ -20,7 +20,7 @@ function! s:VerilogInstance(type,...) abort
   endif
   let cmd = lnum1 . "norm! =="
   execute cmd
-  let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_instance.py " . g:verilog_instance_skip_last_coma
+  let cmd = lnum1 . "," . lnum2 . "!" . " " . s:plugin_dir_path . "/verilog_instance.py " . g:verilog_instance_skip_last_coma . " " . s:verilog_instance_wire_declaration
   execute cmd
 endfunction
 
@@ -30,7 +30,15 @@ nnoremap <silent> <Plug>VerilogInstanceLine :<C-U>set opfunc=<SID>VerilogInstanc
 command! -range VerilogInstance call s:VerilogInstance(<line1>,<line2>)
 
 if !hasmapto('<Plug>VerilogInstance') && maparg('gb','n') ==# ''
+  let s:verilog_instance_wire_declaration = 0
   xmap gb  <Plug>VerilogInstance
   nmap gb  <Plug>VerilogInstance
   nmap gbb <Plug>VerilogInstanceLine
 endif
+
+if !hasmapto('<Plug>VerilogWire') && maparg('ggb','n') ==# ''
+  let s:verilog_instance_wire_declaration = 1
+  xmap ggb  <Plug>VerilogInstance
+  nmap ggb  <Plug>VerilogInstance
+  nmap ggbb <Plug>VerilogInstanceLine
+endif