Mio fpga

src/common/hdl/oh_fifo_async.v

@@ -67,7 +67,29 @@ module oh_fifo_async # (parameter DW        = 104,      //FIFO width
 		      .din			(din[DW-1:0]),
 		      .rd_en			(rd_en));
 	   end // if ((DW==104) & (DEPTH==32))
-      end // block: xilinx   
+	 else if((DW==128) & (DEPTH==32))
+	   begin
+	      fifo_async_128x32
+		fifo (
+		      // Outputs
+		      .full			(full),
+		      .prog_full		(prog_full),
+		      .dout			(dout[DW-1:0]),
+		      .empty			(empty),
+		      .rd_data_count		(rd_count[AW-1:0]),
+		      // Inputs
+		      .rst			(~nreset),
+		      .wr_clk			(wr_clk),
+		      .rd_clk			(rd_clk),
+		      .wr_en			(wr_en),
+		      .din			(din[DW-1:0]),
+		      .rd_en			(rd_en));
+	   end // if ((DW==128) & (DEPTH==32))
+	 else
+	   _INVALID_PARAMETERS_ invalid_parameters();
+       end // block: xilinx
+       else
+	 _INVALID_TARGET_ invalid_target();
    endgenerate
 
 endmodule // oh_fifo_async

src/mio/dv/dut_mio.v

@@ -41,15 +41,18 @@ module dut(/*AUTOARG*/
    //########################################
 
    //wires
-   wire 	     reg_access_in;   
+   wire 	     reg_access_in;
    wire [PW-1:0]     reg_packet_in;
    wire 	     reg_wait_in;
    wire 	     mio_access_in;
-
+   wire [PW-1:0]     mio_packet_out;
+   wire 	     mio_wait_in;
+
    /*AUTOINPUT*/
-   // End of automatics
+
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire			mio_access_out;		// From mio of mio.v
    wire			reg_access_out;		// From mio of mio.v
    wire [PW-1:0]	reg_packet_out;		// From mio of mio.v
    wire			reg_wait_out;		// From mio of mio.v
@@ -73,6 +76,19 @@ module dut(/*AUTOARG*/
    assign reg_packet_in    = packet_in;
    assign reg_wait_in      = wait_in;
 
+
+   emesh_mux #(.N(2),.AW(AW))
+   mux2(// Outputs
+	.wait_out   ({reg_wait_in, mio_wait_in}),
+	.access_out (access_out),
+	.packet_out (packet_out[PW-1:0]),
+	// Inputs
+	.access_in  ({reg_access_out, mio_access_out}),
+	.packet_in  ({reg_packet_out[PW-1:0], mio_packet_out[PW-1:0]}),
+	.wait_in    (wait_in)
+	);
+
+
    //########################################
    //# DUT: MIO IN LOOPBACK
    //########################################
@@ -86,6 +102,10 @@ module dut(/*AUTOARG*/
             .tx_packet	    (tx_packet[NMIO-1:0]),
 	    .tx_wait        (rx_wait),
             .access_in	    (mio_access_in),
+            .access_out	    (mio_access_out),
+	    .packet_out	    (mio_packet_out[]),
+	    .wait_in	    (mio_wait_in),
+
 
     );
     */
@@ -100,8 +120,8 @@ module dut(/*AUTOARG*/
 	.tx_packet			(tx_packet[NMIO-1:0]),	 // Templated
 	.rx_wait			(rx_wait),
 	.wait_out			(wait_out),
-	.access_out			(access_out),
-	.packet_out			(packet_out[PW-1:0]),
+	.access_out			(mio_access_out),	 // Templated
+	.packet_out			(mio_packet_out[PW-1:0]), // Templated
 	.reg_wait_out			(reg_wait_out),
 	.reg_access_out			(reg_access_out),
 	.reg_packet_out			(reg_packet_out[PW-1:0]),
@@ -114,7 +134,7 @@ module dut(/*AUTOARG*/
 	.rx_packet			(tx_packet[NMIO-1:0]),	 // Templated
 	.access_in			(mio_access_in),	 // Templated
 	.packet_in			(packet_in[PW-1:0]),
-	.wait_in			(wait_in),
+	.wait_in			(mio_wait_in),		 // Templated
 	.reg_access_in			(reg_access_in),
 	.reg_packet_in			(reg_packet_in[PW-1:0]),
 	.reg_wait_in			(reg_wait_in));

src/mio/dv/tests/test_reg_read.emf

@@ -0,0 +1,20 @@
+FFEEDDCC_BBAA9988_77665544_05_0080 //EMESH 32 BIT WRITE (DEFAULT)
+DEADBEEF_00000000_00000004_05_0000 //WRITE STATUS
+810d0000_00000000_00000004_04_0000 //READ STATUS
+DEADBEEF_00001048_00000000_05_0000 //CONFIG(AMODE,MSB,DDR,SIZE="64") 
+810d0004_00000000_00000000_04_0000 //READ CONFIG (not supported)
+DEADBEEF_00000000_00000004_05_0000 //WRITE STATUS
+DEADBEEF_00000007_00000008_05_0000 //WRITE CLKDIV
+DEADBEEF_06020400_0000000c_05_0000 //WRITE CLKPHASE
+DEADBEEF_80800000_00000018_05_0000 //WRITE ADDR0
+DEADBEEF_00000000_0000001c_05_0080 //WRITE ADDR1
+22222222_11111111_FFF00000_00_0200 //AMODE 64 BIT WRITE
+810d0000_00000000_00000004_04_0000 //READ STATUS
+44444444_33333333_FFF00000_00_0000 //AMODE 64 BIT WRITE
+66666666_55555555_FFF00000_00_0000 //AMODE 64 BIT WRITE
+88888888_77777777_FFF00000_00_0000 //AMODE 64 BIT WRITE
+aaaaaaaa_99999999_FFF00000_00_0000 //AMODE 64 BIT WRITE
+810d0008_00000000_00000004_04_0100 //READ STATUS
+810d000c_00000000_00000004_04_0100 //READ STATUS
+
+

src/mio/fpga/axi_mio_timing.xdc

@@ -0,0 +1,32 @@
+# Use numbers from here:
+# https://en.wikipedia.org/wiki/Propagation_delay
+# Assume wires are shorter than < 30cm (12")
+
+# slave
+create_clock -period 30.000 -name mio_s_sclk -waveform {0.000 15.000} [get_ports {gpio_p[3]}]
+# assign mio_s_mosi = gpio_in[8];
+set_input_delay  -clock mio_s_sclk -max 2.000            [get_ports {gpio_n[4]}]
+# assign mio_s_miso = gpio_out[9];
+set_output_delay -clock mio_s_sclk -max -add_delay 2.000 [get_ports {gpio_n[5]}]
+# assign mio_s_ss   = gpio_in[10];
+set_input_delay  -clock mio_s_sclk -max 2.000            [get_ports {gpio_p[4]}]
+
+#master
+# assign mio_m_sclk = gpio_out[3];
+# just misses timing for 100 MHz
+create_clock -period 20.000 -name mio_m_sclk -waveform {0.000 10.000} [get_ports {gpio_p[1]}]
+# assign mio_m_mosi = gpio_out[4];
+set_output_delay -clock mio_m_sclk -max -add_delay 2.000 [get_ports {gpio_n[2]}]
+# assign mio_m_miso = gpio_in[5];
+set_input_delay  -clock mio_m_sclk -max 2.000            [get_ports {gpio_n[3]}]
+# assign mio_m_ss   = gpio_out[6];
+set_output_delay -clock mio_m_sclk -max -add_delay 2.000 [get_ports {gpio_p[2]}]
+
+set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks mio_m_sclk]
+
+# pgpio.v pin mapping
+#  for(m=0; m<NGPIO; m=m+2) begin : assign_se_sigs
+#     assign ps_gpio_i[2*m]   = gpio_i_n[m];
+#     assign ps_gpio_i[2*m+1] = gpio_i_n[m+1];
+#     assign ps_gpio_i[2*m+2] = gpio_i_p[m];
+#     assign ps_gpio_i[2*m+3] = gpio_i_p[m+1];

src/mio/fpga/bit2bin.bif

@@ -0,0 +1,6 @@
+the_ROM_image:
+{
+	[bootloader]dummy.elf
+	./system.runs/impl_1/system_wrapper.bit
+}
+

src/mio/fpga/build.sh

@@ -0,0 +1,15 @@
+#!/bin/bash
+
+#clean up
+rm system_wrapper.bit.bin bit2bin.bin
+
+#package IP
+vivado -mode batch -source package.tcl
+
+#create bit stream
+vivado -mode batch -source run.tcl
+
+#xilinx stuff...
+bootgen -image bit2bin.bif -split bin 
+cp system_wrapper.bit.bin parallella.bit.bin
+

src/mio/fpga/clean.sh

@@ -0,0 +1,21 @@
+#!/bin/sh
+rm -rf component.xml
+rm -rf parallella.bit.bin
+rm -rf parallella_mio.cache
+rm -rf parallella_mio.hw
+rm -rf parallella_mio.sim
+rm -rf parallella_mio.xpr
+rm -rf parallella_mio.zip
+rm -rf reports
+rm -rf results
+rm -rf src
+rm -rf system.cache
+rm -rf system.hw
+rm -rf system.runs
+rm -rf system.sim
+rm -rf system.srcs
+rm -rf system_wrapper.bit.bin
+rm -rf system.xpr
+rm -rf vivado*.jou
+rm -rf vivado*.log
+rm -rf xgui

src/mio/fpga/ip_params.tcl

@@ -0,0 +1,26 @@
+# NOTE: See UG1118 for more information
+
+set design parallella_mio
+set projdir ./
+set root "../.."
+set partname "xc7z020clg400-1"
+
+set hdl_files [list \
+	           $root/mio/hdl \
+		   $root/common/hdl/ \
+		   $root/emesh/hdl \
+		   $root/emmu/hdl \
+		   $root/axi/hdl \
+		   $root/emailbox/hdl \
+		   $root/edma/hdl \
+	           $root/elink/hdl \
+	           $root/parallella/hdl \
+		  ]
+
+set ip_files   [list \
+		    $root/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci \
+		    $root/xilibs/ip/fifo_async_128x32/fifo_async_128x32.xci \
+		   ]
+
+set constraints_files []
+

src/mio/fpga/package.tcl

@@ -0,0 +1,3 @@
+#STEP1: DEFINE KEY PARAMETERS
+source ./ip_params.tcl
+source ../../common/fpga/create_ip.tcl

src/mio/fpga/run.tcl

@@ -0,0 +1,12 @@
+
+#STEP1: DEFINE KEY PARAMETERS
+source ./run_params.tcl
+
+#STEP2: CREATE PROJECT AND READ IN FILES
+source ../../common/fpga/system_init.tcl
+
+#STEP 3 (OPTIONAL): EDIT system.bd in VIVADO gui, then go to STEP 4.
+##...
+
+#STEP 4: SYNTEHSIZE AND CREATE BITSTRAM
+source ../../common/fpga/system_build.tcl

src/mio/fpga/run_params.tcl

@@ -0,0 +1,23 @@
+
+#Design name ("system" recommended)
+set design system
+
+#Project directory ("." recommended)
+set projdir ./
+
+#Device name
+set partname "xc7z020clg400-1"
+
+#Paths to all IP blocks to use in Vivado "system.bd"
+
+set ip_repos [list "."]
+
+#All source files
+set hdl_files []
+
+#All constraints files
+set constraints_files [list \
+	../../parallella/fpga/parallella_io.xdc \
+	../../parallella/fpga/parallella_7020_io.xdc \
+	./axi_mio_timing.xdc \
+	]