Skip to content
View aqdarahmad's full-sized avatar
4 followers · 3 following

Achievements

Achievement: YOLOAchievement: Pull Sharkx3

Achievements

Achievement: YOLOAchievement: Pull Sharkx3

Block or report aqdarahmad

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
aqdarahmad/README.md

Hi,I'm Aqdar



Computer Engineering student with a strong passion for hardware design and computer architecture.



Currently Working on Updated version of ALU .

I love UVM, FPGA, Bug Finding,and Embedded systems.

Languages and Tools:

c cplusplus csharp css3 dart flutter html5 java javascript linux mongodb nodejs postman python react

aqdarahmad

 aqdarahmad

aqdarahmad

Pinned Loading

  1. Calculator-GUI-using-java Calculator-GUI-using-java Public

    Java

  2. Design-n-Tb-Code-of-4-bit-BCD-Adder-7-segment-display-16-bit-BCD-adder-8x8-bit-multiplier- Design-n-Tb-Code-of-4-bit-BCD-Adder-7-segment-display-16-bit-BCD-adder-8x8-bit-multiplier- Public

    This repository contains the gate-level design implementations All components are designed using strict gate-level modeling in Verilog/SystemVerilog.

    SystemVerilog

  3. lose-found2-master lose-found2-master Public

    Dart

  4. RISC_V-BMU RISC_V-BMU Public

    SystemVerilog

  5. 32bit-ALU-UVM-Verification 32bit-ALU-UVM-Verification Public

    This repository contains a 32-bit Arithmetic Logic Unit (ALU) fully verified using a Universal Verification Methodology (UVM) environment written in SystemVerilog.

    SystemVerilog