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archita-2005/README.md

Hi, I'm Archita Roy 👋

🎓 ECE Undergraduate @ NIT Silchar | 🧠 GATE Aspirant
💡 Aspiring VLSI Engineer | 📘 Documenting my journey with GitHub

🚀 About Me

  • 🎓 I'm currently a final year Electronics & Communication Engineering student at NIT Silchar
  • 💻 Exploring the core domain: VLSI, Digital Design, RTL, FPGA
  • 🔬 Currently building hands-on projects in Verilog
  • 🧠 Preparing for GATE (ECE) while developing my tech portfolio

📂 Featured Repositories

🚀 RISC-V-32I-5-Stage-Pipeline

A 32-bit 5-Stage Pipelined RISC-V (RV32I) processor implemented in Verilog HDL, featuring IF, ID, EX, MEM, and WB stages, modular datapath and control path, pipeline registers, hazard detection, data forwarding, stalling, flushing, and functional simulation using Xilinx Vivado.

🚀 RISCV-32Bit-Single-Cycle-CPU

A 32-bit Single-Cycle RISC-V (RV32I) processor implemented in Verilog HDL, featuring a modular RTL architecture, instruction fetch/decode/execute datapath, control unit, register file, ALU, data memory, and functional simulation using Xilinx Vivado.

🗄️ Direct_Mapped_Cache_Controller

A 32-bit Direct-Mapped Cache Controller implemented in Verilog HDL, featuring cache hit/miss detection, tag comparison, valid-bit management, FSM-based cache control, cache refill logic, and behavioral main memory simulation in Xilinx Vivado.

🔗 AMBA_AXI4_Memory_Controller

A simplified AMBA AXI4 Memory Controller implemented in Verilog HDL, featuring AXI4-compliant read/write channels, independent Read and Write FSMs, burst transaction support, memory interface logic, and simulation-based verification using Xilinx Vivado.

💻 vlsi-projects-archita

A growing collection of Verilog HDL, RTL Design, Computer Architecture, FPGA, and VLSI projects developed as part of my digital hardware design and verification journey.

🧰 Tools & Technologies

  • 🚀 Advanced RTL Design using Verilog HDL
  • 🚀 RISC-V Processor Design and Computer Architecture
  • 🚀 VLSI Design Flow and CMOS Fabrication
  • 🚀 FPGA Design using Xilinx Vivado
  • 🚀 Embedded Systems and Microcontroller Programming
  • 🚀 GATE ECE Preparation (Digital Electronics, Control Systems, Signal Processing, VLSI)

📬 Connect with Me

🌱 This GitHub profile is my learning diary as I explore the intersection of theory and implementation in VLSI.

Popular repositories Loading

  1. vlsi-projects-archita vlsi-projects-archita Public

    A collection of VLSI and Verilog-based hardware design projects.

    Verilog

  2. archita-2005 archita-2005 Public

  3. RISCV-32Bit-Single-Cycle-CPU RISCV-32Bit-Single-Cycle-CPU Public

    Verilog

  4. Direct_Mapped_Cache_Controller Direct_Mapped_Cache_Controller Public

    32-bit Direct Mapped Cache Controller implemented in Verilog HDL using Xilinx Vivado.

    Verilog

  5. AMBA_AXI4_Memory_Controller AMBA_AXI4_Memory_Controller Public

    RTL implementation of an AMBA AXI4 Memory Controller in Verilog HDL.

    Verilog

  6. RISC-V-32I-5-Stage-Pipeline RISC-V-32I-5-Stage-Pipeline Public

    32-bit Pipelined RISC-V Processor implemented in Verilog HDL.

    Verilog