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core: fix sketch sizes#381

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gibix wants to merge 4 commits intoarduino:mainfrom
gibix:fix/sketch-sizes
Open

core: fix sketch sizes#381
gibix wants to merge 4 commits intoarduino:mainfrom
gibix:fix/sketch-sizes

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@gibix gibix commented Mar 4, 2026

After #350 calculate sketch size in two different way if .llext. stays on flash or relocated

Depends on #385

@gibix gibix force-pushed the fix/sketch-sizes branch 3 times, most recently from 7099b0b to 7f19d86 Compare March 4, 2026 16:48
@gibix gibix changed the title Fix sketch sizes core: fix sketch sizes Mar 4, 2026
@per1234 per1234 added the bug Something isn't working label Mar 5, 2026
@gibix gibix force-pushed the fix/sketch-sizes branch 2 times, most recently from 2643178 to 62155f4 Compare March 5, 2026 08:47
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github-actions bot commented Mar 5, 2026

Built 0.53.2-0.dev+62155f4

CI run FAILED: ❌ niclasense

ArtifactBoardCoreTestsRAMSketchesWarningsErrors
✅* zephyr_contrib ek_ra8d1 📗 ✅*

11.9%

22-
frdm_mcxn947 3 🏷️ ✅*

58.0%

22-
frdm_rw612 1 🏷️ ✅*

83.0%

22-
zephyr_main giga 4 🏷️ ✅*

54.5%

4414-
nano33ble 1 🏷️ ✅*

78.7%

2210-
nano_matter 📗 ✔️*

⚠️ 85.7%

2010(2*)
niclasense 2 🏷️

⚠️ 87.3%

20108
opta 4 🏷️ ✔️*

46.7%

5426(2*)
portentac33 3 🏷️ ✔️*

⚠️ 95.1%

5628(8*)
portentah7 3 🏷️ ✔️*

47.3%

5828(2*)
✅* zephyr_unoq unoq 📗 ✅*

26.3%

5210-
Legend

BoardTestStatus description
🔥 🔥 Test run failed to complete.
🔴 Test completed with unexpected errors.
✔️* 🚫 Test completed with errors, but all are known/expected.
✅* 🟡 Test completed with some warnings; no errors detected.
🟢 Test passed successfully, with no warnings or errors.
🌑 🌑 Test was skipped.

Caution

zephyr_main is blocked due to failures on niclasense!

@gibix gibix force-pushed the fix/sketch-sizes branch 3 times, most recently from f73ca4d to 5547f7d Compare March 5, 2026 14:04
gibix and others added 4 commits March 5, 2026 16:44
Select sections by their ELF flags (SHF_ALLOC, SHF_WRITE) rather than
matching against a hardcoded list of section names. This is more robust
as it automatically handles renamed or custom sections.

- Static mode: SHF_ALLOC + SHF_WRITE (writable RAM sections)
- Dynamic mode: SHF_ALLOC (all loaded sections go to LLEXT heap)
- NO_RELOC: .llext.rodata.noreloc still excluded by name

Signed-off-by: Gilberto Conti <g.conti@arduino.cc>
This commit introduces a mechanism to auto-generate board-specific
properties in a new file called `boards.local.txt` during the build
process. The `build.sh` script now extracts relevant information from
the generated files and updates `boards.local.txt` with properties such
as upload address, maximum sketch size, maximum data size, and
machine-specific flags (architecture, MCU, FPU, float ABI).

The `package_core.yml` workflow has been updated to gather all relevant
fields from each build's local files and append them to the official
'boards.txt' that is released.

Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
The regex-based size calculation using arm-zephyr-eabi-size could not
distinguish between static and dynamic link modes, nor account for
CONFIG_LLEXT_RODATA_NO_RELOC keeping .rodata sections in flash.

Update platform.txt to call check-size instead of arm-zephyr-eabi-size,
and register it as a packaged tool dependency in _common.json.

Signed-off-by: Gilberto Conti <g.conti@arduino.cc>
@gibix gibix force-pushed the fix/sketch-sizes branch from 5547f7d to 1f6aedc Compare March 5, 2026 16:08
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4 participants