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drm: rockchip: DSI fixes for RK3576 dual-display #495

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Merged
HeyMeco merged 2 commits into from
Jun 1, 2026
Merged

drm: rockchip: DSI fixes for RK3576 dual-display #495

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01cbf34
drm/rockchip: rk3576: switch DSI dclk_src from vpll to cpll
mingzhangqun Jun 1, 2026
ae0ddef
drm/rockchip: dw-mipi-dsi2: set panel orientation before device
mingzhangqun Jun 1, 2026
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4 changes: 4 additions & 0 deletions drivers/gpu/drm/rockchip/dw-mipi-dsi2-rockchip.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1497,6 +1497,10 @@ static int dw_mipi_dsi2_connector_init(struct dw_mipi_dsi2 *dsi2)

drm_connector_helper_add(connector,
&dw_mipi_dsi2_connector_helper_funcs);

if (dsi2->panel)
drm_connector_set_orientation_from_panel(connector, dsi2->panel);

ret = drm_connector_attach_encoder(connector, encoder);
if (ret < 0) {
DRM_DEV_ERROR(dev, "Failed to attach encoder: %d\n", ret);
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19 changes: 19 additions & 0 deletions drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -10226,6 +10226,25 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta
ret = vop2_clk_set_parent_extend(vp, vcstate, true);
if (ret < 0)
goto out;

/*
* For RK3576 MIPI/DSI output, switch dclk_src parent from vpll
* to cpll. This prevents DP's vpll reprogramming from breaking
* DSI pixel clock when both displays are active.
* cpll at 1000MHz supports 720x1280@60 exactly (1000/12=83.33MHz).
*/
if (vop2->version == VOP_VERSION_RK3576 &&
(vcstate->output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_MIPI1))) {
struct clk_hw *dclk_hw = __clk_get_hw(vp->dclk);
if (dclk_hw) {
struct clk_hw *src_hw = clk_hw_get_parent(dclk_hw);
if (src_hw) {
struct clk *cpll = __clk_lookup("cpll");
if (cpll)
clk_set_parent(src_hw->clk, cpll);
}
}
}
if (dclk)
dclk_rate = dclk->rate;
else
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