Hardcaml MIPS CPU

Hi! We are Sasha Skvortsov and Mayur Deshpande. As a followup to a class project, we are designing a simple 5-stage MIPS CPU in OCaml via the HardCaml library. You can read more about this project at the CeramicHacker blog.

Code Structure

There are 3 main components to this codebase:

• In lib: source code for the MIPS CPU
• In test: Unit and integration tests for the MIPS CPU
• In the project root: a main.ml file that prints the design from lib into Verilog

How to Use

Coming Soon