GitHub - brysonmarazzi/RISCMachine: A Reduced Instruction Set Computer programmed in Verilog. Each individual component of the cpu has been coded in a modular structure. The code is meant to be ran on a DE1-SoC. This RISC machine is Turing complete.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
DE1_SoC.qsf		DE1_SoC.qsf
FSM.v		FSM.v
RAM.v		RAM.v
alu.v		alu.v
alu_tb.v		alu_tb.v
cpu.v		cpu.v
cpu_tb.v		cpu_tb.v
datapath.v		datapath.v
datapath_tb.v		datapath_tb.v
decoder.v		decoder.v
lab8.qpf		lab8.qpf
lab8_autograder_check.v		lab8_autograder_check.v
lab8_stage2_tb.v		lab8_stage2_tb.v
lab8_top.qsf		lab8_top.qsf
lab8_top.v		lab8_top.v
regfile.v		regfile.v
shifter.v		shifter.v

About

A Reduced Instruction Set Computer programmed in Verilog. Each individual component of the cpu has been coded in a modular structure. The code is meant to be ran on a DE1-SoC. This RISC machine is Turing complete.