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- Fix seek timing: multiply step rate by 1000 to convert msec to usec (was 1000x too fast, matching BubiC-8801MA reference implementation) - Use constant 100µs exec-phase delay in SDL mode instead of rotational-position-based calculation (SDL event system lacks sufficient precision for position tracking) - Disable TC acceptance during PHASE_EXEC in 8MHz mode to prevent premature read termination (Xanadu compat hack only for 4MHz) - Reduce DATA LOST timeout from 30ms to 15ms for tighter DRQ handling - Widen single_exec parameters for 8MHz mode (slice: 4→20 clocks, timeout: 10ms→20ms) so the CPU can complete instructions and handle FDC interrupts reliably at double clock speed Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
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Summary
Closes #35
Test plan
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