I3C Core

This repository provides an I3C Core, which will be:

• compliant with
  • MIPI Alliance Specification for I3C Basic, Version 1.1.1
  • MIPI Alliance Specification for I3C HCI, Version 1.2
  • MIPI Alliance Specification for I3C TCRI, Version 1.0
• operational in both Active and Secondary Controller Mode

A login with MIPI Alliance account is required to access the document on MIPI website.

This repository provides:

• SystemVerilog description of the hardware
• Cocotb/Verilator verification
• UVM tests
• tools

This repository depends on:

• Caliptra RTL

Setup

System requirements

This repository is currently tested on Debian 12 and Ubuntu 22.04. In order to use all features, you need to install:

• RISC-V toolchain == 12.1.0
• Verilator >= 5.012
• LCOV == v1.16
• Verible == v0.0-3624-gd256d779
• Icarus Verilog >= 12.0

Submodules

Make sure submodules are checked out. Use the --recursive flag when cloning, or run the following:

git submodule update --init --recursive

if you already cloned the repository.

Python

A bootstrap script is provided, runnable as ./install.sh which will install pyenv. Then, you can install and activate a python environment with . activate.sh.

The activation script creates a virtual environment with Python3.11 and installs python packages from the requirements.txt file. Python 3.11.0 is recommended and installed for this project.

Verification

More details can be found in verification README. Coverage data is available in GitHub pages.

This core is verified with the following set of tests:

• A set of rapid tests written in cocotb
• Avery I3C VIP based tests
• Selected tests from the Avery I3C Compliance Test Suite

Running all the cocotb tests with make tests will check if the environment is properly configured.

Tools used for the core verification are:

• Simulation:

  • VCS R-2020.12-SP2-8
  • Verilator v5.024

• Lint:

  • Spyglass VC Static U-2023.03-SP2-4

• RDC:

  • Spyglass VC Static U-2023.03-SP2-4
  • MeridianRDC 2022.A.P10.2.RDC for RHEL7.0-64, Rev 189206

Tools

Tools developed for this project are located in tools directory. You can find more detailed information in README of each tool:

• i3c_config - manage configuration and produce header files
• reg_gen - scripts to generate SystemVerilog description from the SystemRDL files
• timing - helper script to estimate timings on the bus
• verible-scripts - scripts to manage configuration and runs of Verible formatter and linter

In thetools verification directory, a noxfile is provided to test the I3C Core Configuration Tool.