Generated Tests 1 and 2 for B5 Converts

Makefile

@@ -11,15 +11,7 @@ ifeq ($(AGGRESSIVENESS), 0)
 	COVER_FLOAT_FLAGS += --partial-output
 endif
 
-ifneq ($(PROCESSED_ONLY),)
-	COVER_FLOAT_FLAGS += --only-processed-vectors
-endif
-
-ifneq ($(SILENT),)
-	COVER_FLOAT_FLAGS += -qq
-endif
-
-MODELS := B1 B2 B3 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B20 B21 B25 B26 B27 B29
+MODELS := B1 B2 B3 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B18 B20 B21 B25 B26 B27 B29
 
 .PHONY: build clean sim all $(MODELS)
 

config.svh

@@ -16,11 +16,11 @@
 // define macros for which models to check coverage for
 // e.g. `define COVER_B1 for model B1
 
-`define COVER_B1
-`define COVER_B2
-`define COVER_B3
-`define COVER_B4
-`define COVER_B5
+// `define COVER_B1
+// `define COVER_B2
+// `define COVER_B3
+// `define COVER_B4
+// `define COVER_B5
 // `define COVER_B6
 // `define COVER_B7
 // `define COVER_B8
@@ -36,14 +36,14 @@
 `define COVER_B18
 `define COVER_B19
 // `define COVER_B20
-`define COVER_B21
-`define COVER_B22
-`define COVER_B23
-`define COVER_B24
+// `define COVER_B21
+// `define COVER_B22
+// `define COVER_B23
+// `define COVER_B24
 // `define COVER_B25
 // `define COVER_B26
 // `define COVER_B27
-`define COVER_B28
+// `define COVER_B28
 // `define COVER_B29
 
 // define macros for which precisions to check coverage for

coverage/coverfloat_pkg.sv

@@ -101,6 +101,12 @@ package coverfloat_pkg;
     parameter int F64_M_BITS   = 52;
     parameter int F128_M_BITS  = 112;
 
+    parameter int F32_FMA_PRE_ADDITION_NF = 2 * F32_M_BITS;
+    parameter int F64_FMA_PRE_ADDITION_NF = 2 * F64_M_BITS;
+    parameter int F128_FMA_PRE_ADDITION_NF = 2 * F128_M_BITS;
+    parameter int F16_FMA_PRE_ADDITION_NF = 2 * F16_M_BITS;
+    parameter int BF16_FMA_PRE_ADDITION_NF = 2 * BF16_M_BITS;
+
     // Precision (p = number of significand bits + 1 implicit bits)
     parameter int F16_P   = F16_M_BITS  + 1;
     parameter int BF16_P  = BF16_M_BITS + 1;
@@ -426,7 +432,32 @@ package coverfloat_pkg;
             longest_seq_of_ones = max_len;
         end
     endfunction
+    function automatic int get_effective_product_exponent(
+        input logic[127:0] a,
+        input logic[127:0] b,
+        input logic[255:0] pre_addition,
+        input logic [7:0] fmt
+    );
+        int shift_one;
 
+        case (fmt)
+            FMT_BF16: begin
+                shift_one = pre_addition[BF16_FMA_PRE_ADDITION_NF+1];
+            end
+            FMT_HALF: begin
+                shift_one = pre_addition[F16_FMA_PRE_ADDITION_NF+1];
+            end
+            FMT_SINGLE: begin
+                shift_one = pre_addition[F32_FMA_PRE_ADDITION_NF+1];
+            end
+            FMT_DOUBLE: begin
+                shift_one = pre_addition[F64_FMA_PRE_ADDITION_NF+1];
+            end
+            FMT_QUAD: begin
+                shift_one = pre_addition[F128_FMA_PRE_ADDITION_NF+1];
+            end
+        endcase
+    endfunction
 
     function automatic int get_product_exponent (
         input logic [127:0] a,

coverage/covergroups/B29.svh

@@ -0,0 +1,141 @@
+covergroup B29_cg (virtual coverfloat_interface CFI);
+
+    option.per_instance = 0;
+
+    F16_input_fmt: coverpoint (CFI.operandFmt == FMT_HALF) {
+        type_option.weight = 0;
+        bins f16 = {1};
+    }
+
+    BF16_input_fmt: coverpoint (CFI.operandFmt == FMT_BF16) {
+        type_option.weight = 0;
+        bins bf16 = {1};
+    }
+
+    F32_input_fmt: coverpoint (CFI.operandFmt == FMT_SINGLE) {
+        type_option.weight = 0;
+        bins f32 = {1};
+    }
+
+    F64_input_fmt: coverpoint (CFI.operandFmt == FMT_DOUBLE) {
+        type_option.weight = 0;
+        bins f64 = {1};
+    }
+
+    F128_input_fmt: coverpoint (CFI.operandFmt == FMT_QUAD) {
+        type_option.weight = 0;
+        bins f128 = {1};
+    }
+    // RFI Instruction
+
+    RFI_op: coverpoint CFI.op {
+        type_option.weight = 0;
+        bins rfi = { OP_RFI };
+    }
+
+    rounding_mode_all: coverpoint CFI.rm {
+        type_option.weight = 0;
+        bins round_near_even   = {ROUND_NEAR_EVEN};
+        bins round_minmag      = {ROUND_MINMAG};
+        bins round_min         = {ROUND_MIN};
+        bins round_max         = {ROUND_MAX};
+        bins round_near_maxmag = {ROUND_NEAR_MAXMAG};
+    }
+
+    F32_sign: coverpoint CFI.result[31] {
+        type_option.weight = 0;
+        bins pos = {0};
+        bins neg = {1};
+    }
+
+    F64_sign: coverpoint CFI.result[63] {
+        type_option.weight = 0;
+        bins pos = {0};
+        bins neg = {1};
+    }
+
+    F128_sign: coverpoint CFI.result[127] {
+        type_option.weight = 0;
+        bins pos = {0};
+        bins neg = {1};
+    }
+
+    F16_sign: coverpoint CFI.result[15] {
+        type_option.weight = 0;
+        bins pos = {0};
+        bins neg = {1};
+    }
+
+    BF16_sign: coverpoint CFI.result[15] {
+        type_option.weight = 0;
+        bins pos = {0};
+        bins neg = {1};
+    }
+
+    BF16_LGS_Combos: coverpoint {
+        CFI.a[BF16_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_BF16)) + 1],
+        CFI.a[BF16_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_BF16))],
+        |(CFI.a & ((64'b1 << (BF16_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_BF16)))) - 1))
+        } {
+        type_option.weight = 0;
+        bins lgs_combos[] = {[3'b000 : 3'b111]};
+    }
+
+    F16_LGS_Combos: coverpoint {
+        CFI.a[F16_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_HALF)) + 1],
+        CFI.a[F16_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_HALF))],
+        |(CFI.a & ((64'b1 << (F16_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_HALF)))) - 1))
+        } {
+        type_option.weight = 0;
+        bins lgs_combos[] = {[3'b000 : 3'b111]};
+    }
+
+    F32_LGS_Combos: coverpoint {
+        CFI.a[F32_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_SINGLE)) + 1],
+        CFI.a[F32_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_SINGLE))],
+        |(CFI.a & ((64'b1 << (F32_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_SINGLE)))) - 1))
+        } {
+        type_option.weight = 0;
+        bins lgs_combos[] = {[3'b000 : 3'b111]};
+    }
+
+
+    F64_LGS_Combos: coverpoint {
+        CFI.a[F64_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_DOUBLE)) + 1],
+        CFI.a[F64_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_DOUBLE))],
+        |(CFI.a & ((64'b1 << (F64_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_DOUBLE)))) - 1))
+        } {
+        type_option.weight = 0;
+        bins lgs_combos[] = {[3'b000 : 3'b111]};
+    }
+
+    F128_LGS_Combos: coverpoint {
+        CFI.a[F128_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_QUAD)) + 1],
+        CFI.a[F128_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_QUAD))],
+        |(CFI.a & ((64'b1 << (F128_M_UPPER - $signed(get_unbiased_exponent(CFI.a, FMT_QUAD)))) - 1))
+        } {
+        type_option.weight = 0;
+        bins lgs_combos[] = {[3'b000 : 3'b111]};
+    }
+
+    `ifdef COVER_F32
+        B5_F32_LGS: cross F32_sign, RFI_op, F32_input_fmt, F32_LGS_Combos, rounding_mode_all;
+    `endif
+
+    `ifdef COVER_F64
+        B5_F64_LGS: cross F64_sign, RFI_op, F64_input_fmt, F64_LGS_Combos, rounding_mode_all;
+    `endif
+
+    `ifdef COVER_F128
+        B5_F128_LGS: cross F128_sign, RFI_op, F128_input_fmt, F128_LGS_Combos, rounding_mode_all;
+    `endif
+
+    `ifdef COVER_F16
+        B5_F16_LGS: cross F16_sign, RFI_op, F16_input_fmt, F16_LGS_Combos, rounding_mode_all;
+    `endif
+
+    `ifdef COVER_BF16
+        B5_BF16_LGS: cross BF16_sign, RFI_op, BF16_input_fmt, BF16_LGS_Combos, rounding_mode_all;
+    `endif
+
+endgroup

docs/B18.adoc

@@ -0,0 +1,93 @@
+= B18 Documentation
+:toc:
+:toclevels: 3
+:sectnums:
+:stem:
+
+== B18: Multiply-Add: Special Events
+
+Aharoni et al.
+
+=== Description
+This model checks different cases where the multipliccaion causes some event in the product while the addition cancels this event
+
+Test 1):: Product: Enumerate on all options for LSB, Guard, and Sticky bit.
+Intermediate Result: Exact (Guard and Sticky are zero)
+
+Test 2):: Product: Take overflow values from (B4) "Overflow".
+Intermediate Result: No overflow
+
+Test 3):: Product: Take underflow values from model (B5) "Underflow".
+Intermediate Result: No underflow
+
+*Number of tests:* 1 E 6
+
+*Precisions Supported:* `BF_16`, `FP_16`, `FP_32`, `FP_64`, `FP_128`
+
+*Operations Supported:* `All`
+
+== Implementation
+
+=== Definitions
+`min_exp`:: The minimum exponent for each precision, where the biased exponent value is 1.
+`lp/hp`:: As specified within the operations section, this test suite will be performing high to low precision converts. `hp` refers to the higher precision input operand for these operations, `lp` refers to the lower precision output of the conversion.
+`m_bits`:: The number of mantissa bits, dependent on the precision.
+`min_sn_exp`:: The smallest possible subnormal value based on the precision, 2^min_exp - m_bits.
+`min_sn`:: The smallest possible subnormal input, 2^(min_exp - m_bits)
+`hp_exp/lp_exp`:: The exponent value for `hp` and `lp` respectively.
+`lp_sn_exp`:: The exponent value corresponding to a subnormal value for `lp`. In any precision, this is 0 when represented as a biased exponent. In most tests, the mathematical operations will be expressed where `lp_sn_exp` is unbiased.
+`lsb_exp`:: The exponent value for the least significant bit.
+`lrs_int`:: The integer representation of the desired Isb, rounding, and guard bit values.
+
+== Operations
+=== Three operands
+* FMADD
+* FMSUB
+* FNMSUB
+* FNMADD
+
+=== General Implementation
+Each test presents a different requirement on the intermediate result and product. Based on this requirement, the appropriate factors for multiplication are chosen and the effective operation is determined. The rounding mode is randomly chosen.
+
+==== Test 1 Product Mantissa Pattern
+[cols="5*"]
+|===
+| lrs_int | LSB | Rounding | Sticky | Intermediate Mantissa
+
+| 1 | 0 | 0 | 1 | pass:[****_****_** 1*]
+| 2 | 0 | 1 | 0 | pass:[****_****_** 10]
+| 3 | 0 | 1 | 1 | pass:[****_****_** 1*]
+| 4 | 1 | 0 | 0 | pass:[****_****_*1 00]
+| 5 | 1 | 0 | 1 | pass:[****_****_*1 0*]
+| 6 | 1 | 1 | 0 | pass:[****_****_*1 10]
+| 7 | 1 | 1 | 1 | pass:[****_****_*1 1*]
+| 8 | 0 | 0 | 0 | pass:[****_****_*0 00]
+
+|===
+
+==== Test 1 Intermediate Mantissa Pattern
+[cols="4*"]
+|===
+|LSB | Rounding | Sticky | Intermediate Mantissa
+
+| * | 0 | 0 | pass:[****_****_** 00]
+
+|===
+
+
+== Specific Test Procedure
+=== Test 1
+Multiplication products were extracted from B5, any random number was added or subtracted with a random sign and random operation. Rounding mode is randomly chosen.
+
+=== Total Test Count
+[cols="3*", options="header"]
+|===
+| Test # | Breakdown | Count
+
+| 1 | (188 * 4) | 752
+| 2 | incomplete | incomplete
+| 3 | incomplete | incomplete
+| *Total Tests* | *700*
+|===
+
+_*Differs from Aharoni test count_