[rocky9_7] History Rebuild through kernel-5.14.0-611.26.1.el9_7

Documentation/driver-api/dpll.rst

@@ -182,26 +182,28 @@ is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
 attribute for each parent dpll device.
 
 Device may also provide ability to adjust a signal phase on a pin.
-If pin phase adjustment is supported, minimal and maximal values that pin
-handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
-with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
+If pin phase adjustment is supported, minimal and maximal values and
+granularity that pin handle shall be provided to the user on
+``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``,
+``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN``
 attributes. Configured phase adjust value is provided with
 ``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
 requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
 
-  =============================== ======================================
-  ``DPLL_A_PIN_ID``               configured pin id
-  ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
-  ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
-  ``DPLL_A_PIN_PHASE_ADJUST``     attr configured value of phase
-                                  adjustment on parent dpll device
-  ``DPLL_A_PIN_PARENT_DEVICE``    nested attribute for requesting
-                                  configuration on given parent dpll
-                                  device
-    ``DPLL_A_PIN_PARENT_ID``      parent dpll device id
-    ``DPLL_A_PIN_PHASE_OFFSET``   attr measured phase difference
-                                  between a pin and parent dpll device
-  =============================== ======================================
+  ================================ ==========================================
+  ``DPLL_A_PIN_ID``                configured pin id
+  ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value
+  ``DPLL_A_PIN_PHASE_ADJUST_MIN``  attr minimum value of phase adjustment
+  ``DPLL_A_PIN_PHASE_ADJUST_MAX``  attr maximum value of phase adjustment
+  ``DPLL_A_PIN_PHASE_ADJUST``      attr configured value of phase
+                                   adjustment on parent dpll device
+  ``DPLL_A_PIN_PARENT_DEVICE``     nested attribute for requesting
+                                   configuration on given parent dpll
+                                   device
+    ``DPLL_A_PIN_PARENT_ID``       parent dpll device id
+    ``DPLL_A_PIN_PHASE_OFFSET``    attr measured phase difference
+                                   between a pin and parent dpll device
+  ================================ ==========================================
 
 All phase related values are provided in pico seconds, which represents
 time difference between signals phase. The negative value means that
@@ -343,6 +345,8 @@ according to attribute purpose.
                                        frequencies
       ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
       ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
+    ``DPLL_A_PIN_PHASE_ADJUST_GRAN``   attr granularity of phase
+                                       adjustment value
     ``DPLL_A_PIN_PHASE_ADJUST_MIN``    attr minimum value of phase
                                        adjustment
     ``DPLL_A_PIN_PHASE_ADJUST_MAX``    attr maximum value of phase

Documentation/netlink/specs/dpll.yaml

@@ -428,6 +428,13 @@ attribute-sets:
         doc: |
           A ratio of high to low state of a SYNC signal pulse embedded
           into base clock frequency. Value is in percents.
+      -
+        name: phase-adjust-gran
+        type: u32
+        doc: |
+          Granularity of phase adjustment, in picoseconds. The value of
+          phase adjustment must be a multiple of this granularity.
+
   -
     name: pin-parent-device
     subset-of: pin
@@ -591,6 +598,7 @@ operations:
             - capabilities
             - parent-device
             - parent-pin
+            - phase-adjust-gran
             - phase-adjust-min
             - phase-adjust-max
             - phase-adjust

Makefile.rhelver

@@ -12,7 +12,7 @@ RHEL_MINOR = 7
 #
 # Use this spot to avoid future merge conflicts.
 # Do not trim this comment.
-RHEL_RELEASE = 611.24.1
+RHEL_RELEASE = 611.26.1
 
 #
 # ZSTREAM

arch/arm64/kvm/sys_regs.c

@@ -1584,6 +1584,7 @@ static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
 		break;
 	case SYS_ID_AA64MMFR2_EL1:
 		val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
+		val &= ~ID_AA64MMFR2_EL1_NV;
 		break;
 	case SYS_ID_MMFR4_EL1:
 		val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
@@ -1911,6 +1912,22 @@ static int set_id_aa64pfr1_el1(struct kvm_vcpu *vcpu,
 	return set_id_reg(vcpu, rd, user_val);
 }
 
+static int set_id_aa64mmfr2_el1(struct kvm_vcpu *vcpu,
+				const struct sys_reg_desc *rd, u64 user_val)
+{
+	u64 hw_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1);
+	u64 nv_mask = ID_AA64MMFR2_EL1_NV_MASK;
+
+	/*
+	 * We made the mistake to expose the now deprecated NV field,
+	 * so allow userspace to write it, but silently ignore it.
+	 */
+	if ((hw_val & nv_mask) == (user_val & nv_mask))
+		user_val &= ~nv_mask;
+
+	return set_id_reg(vcpu, rd, user_val);
+}
+
 /*
  * cpufeature ID register user accessors
  *
@@ -2673,7 +2690,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 					ID_AA64MMFR1_EL1_XNX |
 					ID_AA64MMFR1_EL1_VH |
 					ID_AA64MMFR1_EL1_VMIDBits)),
-	ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 |
+	ID_FILTERED(ID_AA64MMFR2_EL1,
+		    id_aa64mmfr2_el1, ~(ID_AA64MMFR2_EL1_RES0 |
 					ID_AA64MMFR2_EL1_EVT |
 					ID_AA64MMFR2_EL1_FWB |
 					ID_AA64MMFR2_EL1_IDS |

arch/x86/kernel/alternative.c

@@ -2567,3 +2567,6 @@ void __ref text_poke_bp(void *addr, const void *opcode, size_t len, const void *
 	text_poke_loc_init(&tp, addr, opcode, len, emulate);
 	text_poke_bp_batch(&tp, 1);
 }
+
+struct alt_instr __kabi__alt_instr[0];
+EXPORT_SYMBOL_GPL(__kabi__alt_instr);

block/blk-sysfs.c

@@ -710,7 +710,7 @@ queue_attr_store(struct kobject *kobj, struct attribute *attr,
 			return res;
 		}
 
-		res = queue_limits_commit_update_frozen(q, &lim);
+		res = queue_limits_commit_update(q, &lim);
 		if (res)
 			return res;
 		return length;

ciq/ciq_backports/kernel-5.14.0-611.26.1.el9_7/30176bf7.failed

@@ -0,0 +1,179 @@
+dpll: add phase-adjust-gran pin attribute
+
+jira KERNEL-541
+Rebuild_History Non-Buildable kernel-5.14.0-611.26.1.el9_7
+commit-author Ivan Vecera <ivecera@redhat.com>
+commit 30176bf7c871681df506f3165ffe76ec462db991
+Empty-Commit: Cherry-Pick Conflicts during history rebuild.
+Will be included in final tarball splat. Ref for failed cherry-pick at:
+ciq/ciq_backports/kernel-5.14.0-611.26.1.el9_7/30176bf7.failed
+
+Phase-adjust values are currently limited by a min-max range. Some
+hardware requires, for certain pin types, that values be multiples of
+a specific granularity, as in the zl3073x driver.
+
+Add a `phase-adjust-gran` pin attribute and an appropriate field in
+dpll_pin_properties. If set by the driver, use its value to validate
+user-provided phase-adjust values.
+
+	Reviewed-by: Michal Schmidt <mschmidt@redhat.com>
+	Reviewed-by: Petr Oros <poros@redhat.com>
+	Tested-by: Prathosh Satish <Prathosh.Satish@microchip.com>
+	Signed-off-by: Ivan Vecera <ivecera@redhat.com>
+	Reviewed-by: Jiri Pirko <jiri@nvidia.com>
+	Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
+Link: https://patch.msgid.link/20251029153207.178448-2-ivecera@redhat.com
+	Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+(cherry picked from commit 30176bf7c871681df506f3165ffe76ec462db991)
+	Signed-off-by: Jonathan Maple <jmaple@ciq.com>
+
+# Conflicts:
+#	Documentation/netlink/specs/dpll.yaml
+#	include/uapi/linux/dpll.h
+diff --cc Documentation/netlink/specs/dpll.yaml
+index 15651f03d943,78d0724d7e12..000000000000
+--- a/Documentation/netlink/specs/dpll.yaml
++++ b/Documentation/netlink/specs/dpll.yaml
+@@@ -428,6 -432,21 +428,24 @@@ attribute-sets
+          doc: |
+            A ratio of high to low state of a SYNC signal pulse embedded
+            into base clock frequency. Value is in percents.
+++<<<<<<< HEAD
+++=======
++       -
++         name: reference-sync
++         type: nest
++         multi-attr: true
++         nested-attributes: reference-sync
++         doc: |
++           Capable pin provides list of pins that can be bound to create a
++           reference-sync pin pair.
++       -
++         name: phase-adjust-gran
++         type: u32
++         doc: |
++           Granularity of phase adjustment, in picoseconds. The value of
++           phase adjustment must be a multiple of this granularity.
++ 
+++>>>>>>> 30176bf7c871 (dpll: add phase-adjust-gran pin attribute)
+    -
+      name: pin-parent-device
+      subset-of: pin
+diff --cc include/uapi/linux/dpll.h
+index 349e1b3ca1ae,69d35570ac4f..000000000000
+--- a/include/uapi/linux/dpll.h
++++ b/include/uapi/linux/dpll.h
+@@@ -249,6 -250,8 +249,11 @@@ enum dpll_a_pin 
+  	DPLL_A_PIN_ESYNC_FREQUENCY,
+  	DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
+  	DPLL_A_PIN_ESYNC_PULSE,
+++<<<<<<< HEAD
+++=======
++ 	DPLL_A_PIN_REFERENCE_SYNC,
++ 	DPLL_A_PIN_PHASE_ADJUST_GRAN,
+++>>>>>>> 30176bf7c871 (dpll: add phase-adjust-gran pin attribute)
+
+  	__DPLL_A_PIN_MAX,
+  	DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
+diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst
+index 195e1e5d9a58..faf643fe8ac8 100644
+--- a/Documentation/driver-api/dpll.rst
++++ b/Documentation/driver-api/dpll.rst
+@@ -182,26 +182,28 @@ is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET``
+ attribute for each parent dpll device.
+
+ Device may also provide ability to adjust a signal phase on a pin.
+-If pin phase adjustment is supported, minimal and maximal values that pin
+-handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
+-with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
++If pin phase adjustment is supported, minimal and maximal values and
++granularity that pin handle shall be provided to the user on
++``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``,
++``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN``
+ attributes. Configured phase adjust value is provided with
+ ``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
+ requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
+
+-  =============================== ======================================
+-  ``DPLL_A_PIN_ID``               configured pin id
+-  ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
+-  ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
+-  ``DPLL_A_PIN_PHASE_ADJUST``     attr configured value of phase
+-                                  adjustment on parent dpll device
+-  ``DPLL_A_PIN_PARENT_DEVICE``    nested attribute for requesting
+-                                  configuration on given parent dpll
+-                                  device
+-    ``DPLL_A_PIN_PARENT_ID``      parent dpll device id
+-    ``DPLL_A_PIN_PHASE_OFFSET``   attr measured phase difference
+-                                  between a pin and parent dpll device
+-  =============================== ======================================
++  ================================ ==========================================
++  ``DPLL_A_PIN_ID``                configured pin id
++  ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value
++  ``DPLL_A_PIN_PHASE_ADJUST_MIN``  attr minimum value of phase adjustment
++  ``DPLL_A_PIN_PHASE_ADJUST_MAX``  attr maximum value of phase adjustment
++  ``DPLL_A_PIN_PHASE_ADJUST``      attr configured value of phase
++                                   adjustment on parent dpll device
++  ``DPLL_A_PIN_PARENT_DEVICE``     nested attribute for requesting
++                                   configuration on given parent dpll
++                                   device
++    ``DPLL_A_PIN_PARENT_ID``       parent dpll device id
++    ``DPLL_A_PIN_PHASE_OFFSET``    attr measured phase difference
++                                   between a pin and parent dpll device
++  ================================ ==========================================
+
+ All phase related values are provided in pico seconds, which represents
+ time difference between signals phase. The negative value means that
+@@ -343,6 +345,8 @@ according to attribute purpose.
+                                        frequencies
+       ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
+       ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
++    ``DPLL_A_PIN_PHASE_ADJUST_GRAN``   attr granularity of phase
++                                       adjustment value
+     ``DPLL_A_PIN_PHASE_ADJUST_MIN``    attr minimum value of phase
+                                        adjustment
+     ``DPLL_A_PIN_PHASE_ADJUST_MAX``    attr maximum value of phase
+* Unmerged path Documentation/netlink/specs/dpll.yaml
+diff --git a/drivers/dpll/dpll_netlink.c b/drivers/dpll/dpll_netlink.c
+index 4619aaa18b9c..6fdbcf3f2572 100644
+--- a/drivers/dpll/dpll_netlink.c
++++ b/drivers/dpll/dpll_netlink.c
+@@ -557,6 +557,10 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
+ 	ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
+ 	if (ret)
+ 		return ret;
++	if (prop->phase_gran &&
++	    nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN,
++			prop->phase_gran))
++		return -EMSGSIZE;
+ 	if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
+ 			prop->phase_range.min))
+ 		return -EMSGSIZE;
+@@ -1073,7 +1077,13 @@ dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
+ 	if (phase_adj > pin->prop.phase_range.max ||
+ 	    phase_adj < pin->prop.phase_range.min) {
+ 		NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr,
+-				    "phase adjust value not supported");
++				    "phase adjust value of out range");
++		return -EINVAL;
++	}
++	if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) {
++		NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr,
++					"phase adjust value not multiple of %u",
++					pin->prop.phase_gran);
+ 		return -EINVAL;
+ 	}
+
+diff --git a/include/linux/dpll.h b/include/linux/dpll.h
+index 1119b7154b1a..7fced8d451c6 100644
+--- a/include/linux/dpll.h
++++ b/include/linux/dpll.h
+@@ -177,6 +177,7 @@ struct dpll_pin_properties {
+ 	u32 freq_supported_num;
+ 	struct dpll_pin_frequency *freq_supported;
+ 	struct dpll_pin_phase_adjust_range phase_range;
++	u32 phase_gran;
+ };
+
+ #if IS_ENABLED(CONFIG_DPLL)
+* Unmerged path include/uapi/linux/dpll.h