VLSI & Digital Design | Electronics Engineering Student, SVNIT Surat
B.Tech student in Electronics and VLSI Engineering at Sardar Vallabhbhai National Institute of Technology (SVNIT), Surat. Working towards a career in the VLSI/semiconductor industry.
I am currently focused on digital design using Verilog and SystemVerilog — building and properly simulating FSM-based designs, and also in strengthening my problem solving skills.
Verilog-Projects : Collection of digital design projects in Verilog/SystemVerilog, simulated and verified. Includes:
- UART TX/RX system with 16x oversampling
- Synchronous FIFO
- Vending machine FSM (parameterized pricing)
- Mealy sequence detector (overlapping pattern detection)
- Debouncer / pulse filter FSM
- Digital door lock FSM with password update
- 4-floor elevator controller (Moore FSM)
- Shift registers (SIPO, SISO, PISO, PIPO, Universal)
Python Projects : CLI-based applications built while learning object-oriented programming:
- Library Management System
- Bank Account System
- Contact Book
- ATM System
- TICTACTOE Game using NumPy
C and JAVA Projects : Data structures and algorithm practice, including custom implementations of Stacks and Queues, along with problem-solving.
LinkedIn: https://www.linkedin.com/in/dev-gothi/