μTheia is a GF180MCU event-based machine-vision ASIC for motion-pattern classification from EVT2 event streams. The chip receives EVT2 event data and configuration commands over SPI, decodes timestamped events, compresses 320×320 sensor coordinates into a 16×16 spatial grid, bins activity into 16 programmable-duration temporal bins, stores feature windows in SRAM, performs integer MAC scoring against programmable class weights, and reports detections for four programmable classes through SPI or selectable physical debug/output pins.
- Process / flow: GF180MCU, wafer.space MPW, LibreLane/OpenROAD, KLayout, Magic, and Netgen.
- Input stream: EVT2 event-camera words and configuration commands over SPI.
- Feature extraction: 320×320 coordinates are spatially compressed to a 16×16 grid and temporally binned into 16 programmable-duration bins.
- Storage: SRAM-backed feature and weight storage.
- Classifier: Integer MAC scoring for four programmable motion-pattern classes.
- Output / debug: Classification results are available over SPI and through selectable debug/output pins.
- Frequency: 64 MHz on-chip and 32 MHz SPI
Full technical documentation is in the docs/ directory:
| Document | Contents |
|---|---|
docs/architecture.md |
System architecture, block diagram, pipeline stages, memory map, and control flow |
docs/rtl_reference.md |
Per-module RTL reference covering ports, parameters, behavior, and timing |
docs/simulation.md |
cocotb testbenches, utility functions, simulation configs, and waveform viewing |
docs/limitations.md |
Known limitations, incomplete items, implementation status, and future improvements |
The docs/debug_mux_pinout.txt file documents per-bit assignments for the debug bus pages.
Note: Max capacitance violations are mostly pads being checked against the 0.2 pF global limit. The remaining max capacitance violations are all buffers within the clock net, again being checked against the aggressive 0.2 pF global limit. In both cases, all maximum capacitance violations were manually investigated, and the offending cells were checked to be within the maximum capacitances listed in their Liberty files. The maximum slew violations in the slowest corner are all bidirectional (assigned output) pads whose violations were similarly checked against their Liberty file entry and determined to be well within their characterized range.
Read these before running the project for the first time.
- Nix/OpenROAD first-run compile time. The
flake.nixenvironment compiles OpenROAD from source using theleo/gf180mcubranch on the firstnix-shellinvocation. This can take 30–90 minutes, depending on CPU speed. The result is cached locally, so later shell launches are much faster. - PDK setup is required before simulation. Run
make config-pdkonce before RTL or gate-level simulation. Simulation depends on GF180MCU SRAM behavioral models from the PDK. - Gate-level simulation is slow and disk-intensive.
make sim-glcan take several hours, and chip-top/gate-level waveform files can reach tens of gigabytes. Make sure the machine has enough RAM, CPU cores, and free disk space before running long simulations. - Weights must be loaded before inference. After every power cycle, the chip starts in the
BOOTstate and will not classify events until the full weight and threshold load sequence completes:BOOT_REQ→ weight commands →EVT_READS_DONE. If the SPI master loses sync during loading, restart the load from the beginning. - SDF back-annotation is not fully reliable.
make sim-sdfis provided, but timing-accurate simulation is not currently dependable because GF180MCU SRAM Verilog timing models are not consistently present in the open PDK distribution. Icarus may silently fall back to zero-delay functional simulation.
The preferred flow uses the project Nix shell, which provides the required LibreLane/OpenROAD environment.
Install Nix and follow the LibreLane Nix installation instructions. Then activate the shell from the repository root:
nix-shellThe remaining commands assume that this shell is active.
git clone git@github.com:dolphin-530/microTheia.git
cd microTheia
nix-shell
make config-pdk
make sim
make librelane
make copy-final
make sim-glμTheia uses cocotb with Icarus Verilog for RTL and gate-level simulation. Testbenches are located in the cocotb/ directory.
Run the default chip-top sanity test:
make simRun a specific module-level test:
make sim DUT=module_name CONFIG=config_nameIf CONFIG is omitted, the simulation uses the default compile arguments from the Makefile. Configuration files are stored in the configs/ directory.
Run the full RTL simulation suite:
make sim-allRun gate-level simulation from the copied final implementation:
make sim-glNote
Gate-level simulation expects the latest completed implementation to be copied into the final/ directory. After a successful LibreLane run, use make copy-final before running make sim-gl.
Simulation waveforms are generated under cocotb/sim_build/. To open the default waveform view, run:
make sim-viewEnter the Nix environment:
nix-shellRun the physical implementation flow:
make librelaneAfter the flow completes, copy the latest successful run into final/:
make copy-finalmake copy-final only works when the most recent implementation run completed successfully.
Open the completed design in the OpenROAD GUI:
make librelane-openroadOpen the completed design in KLayout:
make librelane-klayoutThis project uses Jan Schiefer's verilog_spi, licensed under the GNU LGPL v2.1.
The local spi_module.v version is based on the jasonwaseq/verilog_spi fork and includes cleanup, lint-related changes, and a non-master fallback that drives safe defaults for SCLK_OUT and SS_OUT when SPI_MASTER == 0.
This repository is based on the wafer.space GF180MCU project template. μTheia targets the default 1x1 wafer.space slot and the provided GF180MCU configuration used by the LibreLane flow in this repository. Other slot sizes and alternate template library combinations are not maintained for this design.
- wafer.space GF180MCU project template
- VLSIDA GF180MCU 3.3 V template
- Google GF180MCU PDK
- GF180MCU SRAM Forge
- Prophesee EVT2 format documentation
- FPGA DVS Gesture Classifier
- GenX320 STM32F746G-DISCO custom firmware
