Implements ALC and balances power in different modes

[rkayakr]

ALC is implemented on two levels
global - any transmission that maxes bridge voltage reading (> 42 watts) trips big reduction

alc_level reduced from 1.0 to .5
per band above band limit
alc_level reduced by .06

A message is written to the console when either alc is activated
In both cases power under limit causes alc_level releases by .01 increase per bridge voltage read cycle (about 100 ms).
For example a small band over limit will fully release in less than 1 s.

Per band maximum watts power limits were added to hw_settings.ini with the label max_watts matching the variable name in the preexisting band structure.
Limits will be different for V2 and V3 versions. For V3 you can use max powers in
https://docs.google.com/document/d/1HvpgnS6zuPcygxmB6lvFZztqSGPLlWYzVGHhytWvQG4/edit?tab=t.0

Power used in ALC limit calculation is immediate when a new voltage is read from the bridge, about every 100 ms.
Power reported for display is also immediate, but smoothed by exponential smoothing to reduce jitter
Previously power was only reported every 100 read_power calls, about once a second

Balancing power at same drive setting
CWR was producing far more power than CW at the same drive level
similar problem with LSB and USB
similar problem with SSB and other modes
Balance settings added to hw_settings.ini and used to balance power.
Defaults are set to 1.0.
  CW/CWR    cw_bal <1.0 reduces of CWR power vs Cw
  USB/LSB   ssb_bal <1.0 reduces LSB power vs USB
  CW/SSB   ssb_val <1.0 reduces SSB power vs other modes
ssb_val now balances SSB with other modes. Previously ssb_val also changed CW output

example: my hw_settings.ini
ssb_val=0.75
cw_bal=0.856
ssb_bal=0.71

[drexjj]

This has too many changes and duplicates part of a previous PR you submitted. Please modify or simplify it and resubmit.