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15 changes: 13 additions & 2 deletions MODULE.bazel
Original file line number Diff line number Diff line change
Expand Up @@ -73,5 +73,16 @@ bazel_dep(name = "rules_java", version = "8.15.1")
#
###############################################################################
bazel_dep(name = "score_tooling", version = "1.1.2")
bazel_dep(name = "score_docs_as_code", version = "3.0.1")
bazel_dep(name = "score_process", version = "1.4.4")
bazel_dep(name = "score_docs_as_code")
git_override(
module_name = "score_docs_as_code",
commit = "21640ab325b3aae147ba4e3e8b5e7ab89fc2e8f5",
remote = "https://github.com/eclipse-score/docs-as-code.git",
)

bazel_dep(name = "score_process")
git_override(
module_name = "score_process",
commit = "5205f7bf4a8919a2280989ef5d12e826065e55cd",
remote = "https://github.com/eclipse-score/process_description.git",
)
Original file line number Diff line number Diff line change
@@ -0,0 +1,47 @@
..
# *******************************************************************************
# Copyright (c) 2025 Contributors to the Eclipse Foundation
#
# See the NOTICE file(s) distributed with this work for additional
# information regarding copyright ownership.
#
# This program and the accompanying materials are made available under the
# terms of the Apache License Version 2.0 which is available at
# https://www.apache.org/licenses/LICENSE-2.0
#
# SPDX-License-Identifier: Apache-2.0
# *******************************************************************************

.. _logging_architecture:

Logging Architecture
====================

.. feat:: Logging
:id: feat__logging
:security: YES
:safety: ASIL_B
:status: valid
:provides: logic_arc_int__log_cpp__logging, logic_arc_int__log_rust__logging_rust
:uses: logic_arc_int__baselibs__json, logic_arc_int__baselibs__filesystem


.. logic_arc_int:: Logging
:id: logic_arc_int__log_cpp__logging
:security: YES
:safety: ASIL_B
:status: valid


.. logic_arc_int:: Logging Rust
:id: logic_arc_int__log_rust__logging_rust
:security: YES
:safety: ASIL_B
:status: valid

.. logic_arc_int_op:: Log
:id: logic_arc_int_op__logging__log
:security: YES
:safety: ASIL_B
:status: valid
:included_by: logic_arc_int__log_cpp__logging
1 change: 1 addition & 0 deletions docs/features/analysis-infra/logging/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -20,4 +20,5 @@ Logging

./mw-fr_logging.rst
./docs/requirements/mw-fr_logging_req.rst
./docs/architecture/index.rst
./docs/glossary.rst
Empty file.
Original file line number Diff line number Diff line change
@@ -0,0 +1,45 @@
..
# *******************************************************************************
# Copyright (c) 2025 Contributors to the Eclipse Foundation
#
# See the NOTICE file(s) distributed with this work for additional
# information regarding copyright ownership.
#
# This program and the accompanying materials are made available under the
# terms of the Apache License Version 2.0 which is available at
# https://www.apache.org/licenses/LICENSE-2.0
#
# SPDX-License-Identifier: Apache-2.0
# *******************************************************************************

.. _platform_architecture:

Tracing Architecture
====================

.. feat:: Tracing
:id: feat__tracing
:security: YES
:safety: QM
:status: valid
:provides: logic_arc_int__tracing__tracing


.. logic_arc_int:: Tracing
:id: logic_arc_int__tracing__tracing
:security: YES
:safety: ASIL_B
:status: valid

.. needarch::
:scale: 50
:align: center

{{ draw_interface(need(), needs) }}

.. logic_arc_int_op:: Trace
:id: logic_arc_int_op__tracing__trace
:security: YES
:safety: ASIL_B
:status: valid
:included_by: logic_arc_int__tracing__tracing
Empty file.
Empty file.
Empty file.
Empty file.
2 changes: 2 additions & 0 deletions docs/features/analysis-infra/tracing/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -17,3 +17,5 @@ Tracing

.. toctree::
:maxdepth: 1

./docs/architecture/index.rst
3 changes: 1 addition & 2 deletions docs/features/baselibs/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -89,8 +89,7 @@ Static Architecture
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__baselibs__json, logic_arc_int__baselibs__memory_shared, logic_arc_int__baselibs__message_passing, logic_arc_int__baselibs__result, logic_arc_int__baselibs__bit_manipulation, logic_arc_int__baselibs__bit_mask_operator, logic_arc_int__baselibs__dynamic_array, logic_arc_int__baselibs__intrusive_list, logic_arc_int__baselibs__filesystem, logic_arc_int__baselibs__utils_base64, logic_arc_int__baselibs__utils_scoped_op, logic_arc_int__baselibs__promise, logic_arc_int__baselibs__future, logic_arc_int__baselibs__shared_future, logic_arc_int__baselibs__executor, logic_arc_int__baselibs__task, logic_arc_int__baselibs__task_result, logic_arc_int__baselibs__synchronized_queue, logic_arc_int__baselibs__condition_variable, logic_arc_int__safecpp__aborts_upon_ex, logic_arc_int__safecpp__coverage_termination, logic_arc_int__baselibs__safemath, logic_arc_int__baselibs__safeatomics, logic_arc_int__baselibs__scoped_function, logic_arc_int__baselibs__string_view
:consists_of: comp__com_configuration, comp__com_ipc_binding, comp__com_mock_binding, comp__com_frontend
:provides: logic_arc_int__baselibs__json, logic_arc_int__baselibs__memory_shared, logic_arc_int__baselibs__message_passing, logic_arc_int__baselibs__result, logic_arc_int__baselibs__bit_manipulation, logic_arc_int__baselibs__bit_mask_operator, logic_arc_int__baselibs__dynamic_array, logic_arc_int__baselibs__intrusive_list, logic_arc_int__baselibs__filesystem, logic_arc_int__baselibs__utils_base64, logic_arc_int__baselibs__utils_scoped_op, logic_arc_int__baselibs__promise, logic_arc_int__baselibs__future, logic_arc_int__baselibs__shared_future, logic_arc_int__baselibs__executor, logic_arc_int__baselibs__task, logic_arc_int__baselibs__task_result, logic_arc_int__baselibs__synchronized_queue, logic_arc_int__baselibs__condition_variable, logic_arc_int__safecpp__aborts_upon_ex, logic_arc_int__safecpp__coverage_termination, logic_arc_int__baselibs__safemath, logic_arc_int__baselibs__safeatomics, logic_arc_int__baselibs__scoped_function, logic_arc_int__baselibs__string_view

.. feat_arc_sta:: Baselibs Static View
:id: feat_arc_sta__baselibs__static_view_arch
Expand Down
3 changes: 1 addition & 2 deletions docs/features/communication/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,7 @@ This ensures a stable public API, independent of the underlying binding(s). At t
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__communication__user
:consists_of: comp__com_configuration, comp__com_ipc_binding, comp__com_mock_binding, comp__com_frontend
:provides: logic_arc_int__communication__user

.. feat_arc_sta:: Feature Architecture Communication
:id: feat_arc_sta__com__communication
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -100,8 +100,7 @@ Static Architecture
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__feo__activity, logic_arc_int__feo__prim_agent, logic_arc_int__feo__sec_agent, logic_arc_int__feo__lifecycle
:consists_of: comp__feo_main
:provides: logic_arc_int__feo__activity, logic_arc_int__feo__prim_agent, logic_arc_int__feo__sec_agent, logic_arc_int__feo__lifecycle

.. feat_arc_sta:: Static Architecture
:id: feat_arc_sta__feo__main
Expand Down
3 changes: 1 addition & 2 deletions docs/features/lifecycle/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,7 @@ Lifecycle
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__lifecycle__lifecycle_if, logic_arc_int__lifecycle__controlif, logic_arc_int__lifecycle__alive_if, logic_arc_int__lifecycle__logical_monitor_if, logic_arc_int__lifecycle__deadline_monitor_if
:consists_of: comp__lifecycle_launch_manager, comp__lifecycle_healthmonitor
:provides: logic_arc_int__lifecycle__lifecycle_if, logic_arc_int__lifecycle__controlif, logic_arc_int__lifecycle__alive_if, logic_arc_int__lifecycle__logical_monitor_if, logic_arc_int__lifecycle__deadline_monitor_if

Feature Flag
============
Expand Down
3 changes: 1 addition & 2 deletions docs/features/orchestration/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,7 @@ Feature Architecture
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__orchestration__user, logic_arc_int__orchestration__design, logic_arc_int__orchestration__deployment
:consists_of: comp__orchestrator
:provides: logic_arc_int__orchestration__user, logic_arc_int__orchestration__design, logic_arc_int__orchestration__deployment


Overview
Expand Down
4 changes: 2 additions & 2 deletions docs/features/persistency/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -31,15 +31,15 @@ Architecture
:security: YES
:safety: ASIL_B
:status: valid
:includes: logic_arc_int__persistency__interface
:consists_of: comp__persistency_kvs
:provides: logic_arc_int__persistency__interface

.. comp:: persistency::kvs
:id: comp__persistency_kvs
:security: YES
:safety: ASIL_B
:status: valid
:implements: logic_arc_int__persistency__interface
:belongs_to: feat__persistency



Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ Static Architecture
:status: valid
:tags: baselibs_bit_manipulation
:implements: logic_arc_int__baselibs__bit_manipulation,logic_arc_int__baselibs__bit_mask_operator
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ Static Architecture
:status: valid
:tags: baselibs_concurrency
:implements: logic_arc_int__baselibs__promise, logic_arc_int__baselibs__future, logic_arc_int__baselibs__shared_future, logic_arc_int__baselibs__executor, logic_arc_int__baselibs__task, logic_arc_int__baselibs__task_result, logic_arc_int__baselibs__synchronized_queue, logic_arc_int__baselibs__condition_variable
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,7 @@ Static Architecture
:status: valid
:tags: baselibs_containers
:implements: logic_arc_int__baselibs__dynamic_array, logic_arc_int__baselibs__intrusive_list

:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ Static Architecture
:status: valid
:tags: baselibs_filesystem
:implements: logic_arc_int__baselibs__filesystem
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
5 changes: 3 additions & 2 deletions docs/modules/baselibs/json/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,7 @@ Static Architecture
:status: valid
:implements: logic_arc_int__baselibs__json
:consists_of: comp__baselibs_json_wrapper, comp__baselibs_nlohman_json

:belongs_to: feat__baselibs

.. comp_arc_sta:: JSON Static view
:id: comp_arc_sta__baselibs__json
Expand Down Expand Up @@ -134,10 +134,11 @@ Lower Level Components
:safety: ASIL_B
:status: valid
:implements: logic_arc_int__baselibs__json

:belongs_to: feat__baselibs

.. comp:: nlohman-JSON
:id: comp__baselibs_nlohman_json
:security: YES
:safety: ASIL_B
:status: valid
:belongs_to: feat__baselibs
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ Static Architecture
:status: valid
:tags: baselibs_safecpp
:implements: logic_arc_int__safecpp__aborts_upon_ex, logic_arc_int__safecpp__coverage_termination, logic_arc_int__baselibs__safemath, logic_arc_int__baselibs__safeatomics, logic_arc_int__baselibs__scoped_function, logic_arc_int__baselibs__string_view
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ Memory Shared Component Architecture
:status: valid
:implements: logic_arc_int__baselibs__memory_shared
:uses: logic_arc_int__os__fcntl, logic_arc_int__os__stat, logic_arc_int__os__mman
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ Message Passing Component Architecture
:status: valid
:implements: logic_arc_int__baselibs__message_passing
:uses: logic_arc_int__os__message_passing
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
1 change: 1 addition & 0 deletions docs/modules/baselibs/result/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ Static Architecture
:status: valid
:tags: baselibs_result
:implements: logic_arc_int__baselibs__result
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ Static Architecture
:status: valid
:tags: baselibs_static_reflection_serialization
:implements: logic_arc_int__baselibs__static_reflection,logic_arc_int__baselibs__generic_serial,logic_arc_int__baselibs__log_serial
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
1 change: 1 addition & 0 deletions docs/modules/baselibs/utils/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ Static Architecture
:status: valid
:tags: baselibs_utils
:implements: logic_arc_int__baselibs__utils_base64,logic_arc_int__baselibs__utils_scoped_op
:belongs_to: feat__baselibs

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ Configuration Component Architecture
:safety: ASIL_B
:status: valid
:uses: logic_arc_int__logging__logging
:belongs_to: feat__com_communication

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ Frontend Component Architecture
:status: valid
:implements: logic_arc_int__communication__user
:uses: logic_arc_int__logging__logging, logic_arc_int__tracing__tracing

:belongs_to: feat__com_communication

.. comp_arc_sta:: mw::com Frontend Architecture
:id: comp_arc_sta__com__frontend
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ IPC Binding Component Architecture
:safety: ASIL_B
:status: valid
:uses: logic_arc_int__logging__logging, logic_arc_int__tracing__tracing, logic_arc_int__baselibs__memory_shared, logic_arc_int__baselibs__message_passing, logic_arc_int__baselibs__json
:belongs_to: feat__com_communication

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ Mock Binding Component Architecture
:safety: ASIL_B
:status: valid
:uses: logic_arc_int__logging__logging
:belongs_to: feat__com_communication

.. needarch::
:scale: 50
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,7 @@ Static Architecture
:security: YES
:safety: ASIL_B
:status: valid
:belongs_to: feat__feo

.. comp_arc_sta:: Static Architecture
:id: comp_arc_sta__feo__main
Expand Down
3 changes: 2 additions & 1 deletion docs/modules/lifecycle/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ Lifecycle
:implements: logic_arc_int__lifecycle__controlif, logic_arc_int__lifecycle__alive_if
:uses: logic_arc_int__logging__logging, logic_arc_int__baselibs__json, logic_arc_int__os__unistd, logic_arc_int__lifecycle__lifecycle_if
:security: NO

:belongs_to: feat__lifecycle

.. comp_arc_sta:: Launch Manager Static View
:id: comp_arc_sta__lifecycle__launch_manager
Expand All @@ -68,6 +68,7 @@ Lifecycle
:security: NO
:implements: logic_arc_int__lifecycle__deadline_monitor_if,logic_arc_int__lifecycle__logical_monitor_if
:uses: logic_arc_int__lifecycle__alive_if
:belongs_to: feat__lifecycle

.. comp_arc_sta:: Health Monitor Static View
:id: comp_arc_sta__lifecycle__healthmonitor
Expand Down
1 change: 1 addition & 0 deletions docs/modules/logging/logging/docs/architecture/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ Component Architecture
:safety: ASIL_B
:status: valid
:implements: logic_arc_int__logging__logging
:belongs_to: feat__logging

.. comp_arc_sta:: Logging
:id: comp_arc_sta__logging__logging
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@ The components are designed to cover the expectations from the feature architect
:safety: ASIL_B
:status: valid
:uses: logic_arc_int__logging__logging, logic_arc_int__tracing__tracing
:belongs_to: feat__orchestration


.. comp_arc_sta:: Executor
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,7 @@ The components are designed to cover the expectations from the feature architect
:implements: logic_arc_int__orchestration__user, logic_arc_int__orchestration__deployment, logic_arc_int__orchestration__design
:uses: logic_arc_int__logging__logging, logic_arc_int__tracing__tracing, logic_arc_int__communication__user
:consists_of: comp__orch_design_impl, comp__orch_deployment_impl
:belongs_to: feat__orchestration

.. needarch::
:scale: 50
Expand Down Expand Up @@ -188,13 +189,15 @@ Interfaces
:safety: ASIL_B
:security: NO
:implements: logic_arc_int__orchestration__design
:belongs_to: feat__orchestration

.. comp:: Deployment
:id: comp__orch_deployment_impl
:status: valid
:safety: ASIL_B
:security: NO
:implements: logic_arc_int__orchestration__deployment
:belongs_to: feat__orchestration

.. Operations

Expand Down
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