ports/risc-v32/gnu: Add initial ESP32-C6 bare-metal ThreadX bring-up …

[alieissa-commits]

Summary

This PR adds an initial bare-metal Eclipse ThreadX bring-up example for the Espressif ESP32-C6 microcontroller (ESP32-C6-DevKitC-1) under ports/risc-v32/gnu/example_build/esp32c6/.

It provides the basic hardware adaptation layer, memory map, build scripts, third-party licensing compliance, and a validation application demonstrating ThreadX thread creation and mutex synchronization on RISC-V32.

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Key Changes & Implementations

1. Build System & Toolchain

• CMakeLists.txt & cmake/esp32c6-toolchain.cmake: Cross-compilation support using riscv32-esp-elf-gcc (-march=rv32imac_zicsr_zifencei -mabi=ilp32). Includes post-build esptool.py elf2image generation (esp32c6_demo.bin).

2. Assembly Boot & Trap Infrastructure

• entry.S: Initial CPU setup clearing Machine Interrupts (csrc mstatus, 8), setting up Global Pointer (gp), zeroing .bss, enforcing Direct Mode mtvec (Mode 0), and jumping to c6_startup.
• vectors.S: Trap vector table pre-allocating 128-byte stack frames required by ThreadX RISC-V context save (_tx_thread_context_save), dispatching interrupts to C, and restoring thread context (_tx_thread_context_restore).
• tx_initialize_low_level.S: Assembly hook allocating stack space to preserve ra across platform C driver initialization (esp32c6_platform_init).

3. Memory Map & Bootloader Validation

• link.ld: Configured for ESP32-C6 512 KB SRAM (0x40800000). Placed KEEP(*(.rodata_desc .rodata_desc.*)) at byte offset 0x20 of segment 0 so Espressif's 2nd-stage bootloader validates esp_app_desc_t (0xABCD5432 magic word). Defines _tx_initialize_unused_memory at heap boundary.

4. Platform Hardware Drivers (platform/)

• console.c: UART driver using Espressif ROM API (esp_rom_output_tx_one_char) with \n $\rightarrow$ \r\n line normalization.
• interrupt.c: Configures PCR INTMTX bus clock (0x60096090), PLIC priority levels, CPU interrupt thresholds, and mie.MEIE/mie.MTIE CSR bits. Implements RISC-V PLIC Claim/Complete transaction dispatching via PLIC_MXINT_CLAIM_REG (0x20001094).
• systimer.c: Links pinned ESP-IDF systimer_hal.c, connects Alarm 0 to 16 MHz Counter 0, takes hardware snapshots, and reloads periodic 10ms target values.
• startup.c: Defines esp_app_desc_t, unlocks/disables hardware LP Watchdog Timer (LP_WDT), and hands off execution to tx_kernel_enter().

5. Application Demo & Compliance

• demo_threadx.c: ThreadX kernel validation demo creating demo_mutex, thread_0, and thread_1 with 16-byte aligned static RISC-V stack buffers.
• NOTICE.md: Formal third-party IP attribution file following Eclipse Foundation and Apache 2.0 standards for Espressif Systems, 10xEngineers, and Zephyr RTOS.
• README.md: Build, flash, serial monitor, and OpenOCD/GDB debugging instructions.

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Known Technical Issues & Status (For Future Development)

Warning

This bring-up example is an initial foundation and has active hardware tick issues documented in README.md:

1. Standalone Reset Behavior: On physical power-on without JTAG attached, the board exhibits periodic reset behavior and shows no output.
2. Scheduler Idle Wait: During JTAG debugging with OpenOCD/GDB, execution reaches thread_0_entry. However, after calling tx_thread_sleep(), the ThreadX scheduler remains in _tx_thread_schedule_loop because PLIC external interrupts are not advancing _tx_timer_system_clock.

Recommended Next Steps

As outlined in [threadx_ESP32C6_native_WIFI_plan.md]:

• Replace the custom platform/systimer.c implementation with a pinned ESP-IDF esp_timer framework component import (esp_timer_systimer.c / systimer_hal.c) or use the native CPU RISC-V Machine Timer (mtimecmp / MTIE).

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Verification Performed

• Clean compilation with riscv32-esp-elf-gcc 15.2.0.
• Post-build binary generation with esptool.py elf2image.
• Verified SP, GP, vector alignment, and memory sections in esp32c6_demo.elf.
• Tested OpenOCD JTAG connection and GDB symbols loading.