fix(timing): correct DMA speed, RETI IME enable, and DMA start delay#21

Merged

eddmann merged 7 commits into

mainfrom

claude/fix-rom-check-tests-011CUvhrwoDuE1ENDgvstnSS

Nov 9, 2025

Commits on Nov 9, 2025

fix(timing): correct DMA speed, RETI IME enable, and DMA start delay
claude
committed
refactor(cpu): implement M-cycle accurate CPU execution
claude
committed
fix(cpu): correct instruction cycle timing for JP and LD (HL+/-)
claude
committed
fix(cpu): add internal cycle delays for SP-related instructions
claude
committed
fix(cpu): correct POP instruction timing by removing incorrect internal delay
claude
committed
fix(cpu): add missing condition check cycle to conditional RET instructions
claude
committed
fix(cpu): implement handlers for all illegal/undefined opcodes
claude
committed