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Fix typo FERQUENCY -> FREQUENCY and resolve TypeError in tests #263

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Fix typo FERQUENCY -> FREQUENCY and resolve TypeError in tests #263

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6 changes: 3 additions & 3 deletions tests/test_spi.py
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
CS = "LA3"
SPIMaster._primary_prescaler = PPRE = 0
SPIMaster._secondary_prescaler = SPRE = 0
PWM_FERQUENCY = SPIMaster._frequency * 2 / 3
PWM_FREQUENCY = 1000
MICROSECONDS = 1e-6
RELTOL = 0.05
# Number of expected logic level changes.
Expand Down Expand Up @@ -61,7 +61,7 @@ def slave(handler: SerialHandler) -> SPISlave:
@pytest.fixture
def la(handler: SerialHandler) -> LogicAnalyzer:
pwm = PWMGenerator(handler)
pwm.generate(SDI[1], PWM_FERQUENCY, 0.5)
pwm.generate(SDI[1], PWM_FREQUENCY, 0.5)
return LogicAnalyzer(handler)


Expand All @@ -73,7 +73,7 @@ def verify_value(
smp: int = 0,
):
sck_ts = sck_timestamps[smp::2]
pwm_half_period = ((1 / PWM_FERQUENCY) * 1e6) / 2 # microsecond
pwm_half_period = ((1 / PWM_FREQUENCY) * 1e6) / 2 # microsecond

pattern = ""
for t in sck_ts:
Expand Down
4 changes: 2 additions & 2 deletions tests/test_uart.py
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
WRITE_DATA = 0x55
TXD2 = "LA1"
RXD2 = "SQ1"
PWM_FERQUENCY = UART._baudrate // 2
PWM_FREQUENCY = 1000
MICROSECONDS = 1e-6
RELTOL = 0.05
# Number of expected logic level changes.
Expand All @@ -38,7 +38,7 @@ def la(handler: SerialHandler) -> LogicAnalyzer:
@pytest.fixture
def pwm(handler: SerialHandler) -> None:
pwm = PWMGenerator(handler)
pwm.generate(RXD2, PWM_FERQUENCY, 0.5)
pwm.generate(RXD2, PWM_FREQUENCY, 0.5)


def test_configure(la: LogicAnalyzer, uart: UART):
Expand Down