Verilog_Experiment_CISC

it works

选择比努力重要

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
.gitattributes		.gitattributes
.gitignore		.gitignore
CISC_TOP_MODULE.v		CISC_TOP_MODULE.v
CISC_TOP_MODULE.vwf		CISC_TOP_MODULE.vwf
CISC_TOP_MODULE_ROM.mif		CISC_TOP_MODULE_ROM.mif
CISC_TOP_MODULE_ROM_1.mif		CISC_TOP_MODULE_ROM_1.mif
CISC_TOP_MODULE_testpro_2.mif		CISC_TOP_MODULE_testpro_2.mif
MPC_ROM.v		MPC_ROM.v
MPC_ROM_bb.v		MPC_ROM_bb.v
RAM0.v		RAM0.v
RAM0_bb.v		RAM0_bb.v
README.md		README.md
ROM0.qip		ROM0.qip
ROM0.v		ROM0.v
ROM0_bb.v		ROM0_bb.v
TOP_SIMULATION.vwf		TOP_SIMULATION.vwf
address_reg.v		address_reg.v
alu.v		alu.v
alu.v.bak		alu.v.bak
in_out.v		in_out.v
in_out.v.bak		in_out.v.bak
instruction_reg.v		instruction_reg.v
lpm_rom0.v		lpm_rom0.v
lpm_rom0_bb.v		lpm_rom0_bb.v
memory.v		memory.v
memory.vwf		memory.vwf
mpcu.v		mpcu.v
mpcu.vwf		mpcu.vwf
mpcu_rom.vwf		mpcu_rom.vwf
port.vwf		port.vwf
program_cnt.v		program_cnt.v
register.v		register.v
sequential_gen.v		sequential_gen.v
test_mpcu_rom.v		test_mpcu_rom.v
wcxb.mif		wcxb.mif

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