rk_gpio: implement PIC masking methods and mask unhandled IRQs#2197
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rk_gpio: implement PIC masking methods and mask unhandled IRQs#2197b1nc0d3x wants to merge 1 commit into
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The Rockchip GPIO controller implements PIC operations for the INTRNG framework but is missing four masking methods that INTRNG calls during the filter/ithread handoff: pic_disable_intr, pic_enable_intr, pic_pre_ithread, pic_post_ithread. Without them, level-sensitive interrupt sources connected to a Rockchip GPIO pin re-fire continuously while their ithread runs. On a RockPro64 with a FUSB302B Type-C controller (i2c) attached to gpio1 INT_N, the system enters a ~210 kHz interrupt storm the moment the fusb302 driver attaches and INT_N goes low. Two complementary changes: 1. Add the four pic_disable_intr/pic_enable_intr/pic_pre_ithread/ pic_post_ithread method bodies. Each toggles the pin's RK_GPIO_INTMASK bit so the source is masked during the in-flight ithread window and unmasked on return, honouring the generic INTRNG mask/unmask sequence. 2. When the GPIO IRQ filter dispatches a pin and finds no consumer registered, mask the pin at the controller (INTMASK=1, INTEN=0) before continuing. Level-triggered sources keep asserting until acked, so a single stuck pin used to flood the console with thousands of "Interrupt pin=N unhandled" lines per second. The mask survives until something re-attaches and re-enables the IRQ via the standard pic_enable_intr path. Affects all level-triggered IRQs on Rockchip GPIO banks; edge- triggered IRQs were already self-acking and unaffected. Signed-off-by: Kyle Crenshaw <B1nc0d3x@gmail.com>
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Summary
The Rockchip GPIO controller implements PIC operations for the INTRNG framework but is missing four masking methods that INTRNG calls during the filter / ithread handoff:
pic_disable_intrpic_enable_intrpic_pre_ithreadpic_post_ithreadWithout them, level-sensitive interrupt sources connected to a Rockchip GPIO pin re-fire continuously while their ithread runs. On a RockPro64 with a FUSB302B Type-C controller (i2c) attached to gpio1 INT_N, the system enters a ~210 kHz interrupt storm the moment the fusb302 driver attaches and INT_N goes low. Observed via:
Edge-triggered GPIO IRQs were already self-acking and unaffected.
Two complementary changes:
Add the four
pic_disable_intr/pic_enable_intr/pic_pre_ithread/pic_post_ithreadmethod bodies. Each toggles the pin'sRK_GPIO_INTMASKbit so the source is masked during the in-flight ithread window and unmasked on return. This honours the generic INTRNG mask/unmask sequence and mirrors what other arm64 GPIO drivers do (qoriq_gpio, bcm2835_gpio).When the GPIO IRQ filter dispatches a pin and finds no consumer registered, mask the pin at the controller (INTMASK=1, INTEN=0) before continuing. Level-triggered sources keep asserting until acked, so a single stuck pin (e.g. fusb302 INT_N during attach races or after detach) used to flood the console with thousands of "Interrupt pin=N unhandled" lines per second. The mask survives until something re-attaches and re-enables the IRQ via the standard
pic_enable_intrpath. The single warning line is preserved (now reading "unhandled -- masked") so the underlying issue is still visible.Test plan
top -SHshowsswi1:gpio1pinned. After: 0 spurious IRQs at steady state; pin masks correctly after a detach.Suggested reviewers
manu,mhorne,andrew,mmel— arm64 / Rockchip / INTRNG maintainers pergit log. Not @-mentioned to avoid spam if the GitHub handles don't match; happy to ping on request.Notes
First in a series of patches landing the RockPro64 USB-C DisplayPort + audio path. Successor patches (
drm_fb_helperhotplug fix,usbcPD framework,fusb302,rk_typec_phyDP altmode,rk_cdn_dp) will follow in their own PRs after this one gets a sign-of-life from a reviewer.This patch is independent of the rest of that series and useful on its own for anyone running a Rockchip board with a level-triggered GPIO interrupt source.
Author: Kyle Crenshaw <B1nc0d3x@gmail.com>