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Some VHDL preprocessors may use @@ for their own callouts, so use a different prefix internally lest we filter out those callouts.
To work around VHDL's strict comma rules in PORT MAP and GENERIC
MAP statements and allow simple copy-pasting of new ports near
the end of the port map, designers sometimes write this:
PORT MAP (
port1 => '1'
,port2 => '0'
,port3 => open
)
Add a regex to undo this hack and move the comma back to the end
of the previous line.
The regexes that detect an assignment statement did not match on vector assignments with a range, such as vector(0 to 2) <= some_input or some_other_input; and as such the continuation lines did not get indented at all. Fix this by adding loose matches for bit ranges to the regexes.
During processing of multiline assignments, add a marker in line with the assignment, then during sign alignment align those markers together with the actual assigment. As a side effect, global sign alignment no longer ends the current aligned block on every multiline assignment but now treats multiline assignments the same way as single line assignments, grouping consecutive groups of assignments into a single aligned block.
Contributor
Author
|
Let me know if you'd like me to create issues for the indentation fixes. |
Owner
|
Thanks for this PR. I noticed that one unit test failed ( CONSTANT Vcc : SIGNAL := --logic 1 constant
'1';
CONSTANT zero4 : bit_vector(0 TO 3) :=--test
('0', '0', '0', '0');The expected behavior would be: CONSTANT Vcc : SIGNAL := --logic 1 constant
'1';
CONSTANT zero4 : bit_vector(0 TO 3) := --test
('0', '0', '0', '0'); |
Contributor
Author
|
Sorry for the long delay, busy with other work stuff right now :/ |
Owner
|
I've added the jest into the github action. So if you merge master into your pr, github will check for you automatically. |
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Improve indentation around multiline assignments, comma fixup feature, plus some minor updates.