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[WAVE-24 DRY-RUN] feat(silicon): gf16_dot4_wallace popcount tree · Charter Rule depth fix · DO NOT MERGE PRE-TTSKY26c #36

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[WAVE-24 DRY-RUN] feat(silicon): gf16_dot4_wallace popcount tree · Charter Rule depth fix · DO NOT MERGE PRE-TTSKY26c #36

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302 changes: 302 additions & 0 deletions sim/tb_gf16_dot4_wallace.v
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// SPDX-License-Identifier: Apache-2.0
//
// ============================================================
// sim/tb_gf16_dot4_wallace.v
// Testbench for src/gf16_dot4_wallace.v
// Wave-24 RVR-017 dry-run — Change C Wallace-tree popcount
//
// Test plan:
// 12 corner cases (named vectors):
// TC-01 All-zero inputs -> result = 0x0000
// TC-02 All-positive, unit -> a·b = 1.0×4 = 4.0
// TC-03 All-negative mantissa -> signed products sum
// TC-04 Alternating sign -> partial cancellation
// TC-05 phi-derived 0x47C0 -> phi-structured sentinel
// TC-06 Sentinel pair (1.0, -1.0) dot (1.0, -1.0, 1.0, -1.0) -> 4.0
// TC-07 All +Inf -> result = +Inf
// TC-08 Inf XOR NaN -> result = NaN
// TC-09 Zero dot non-zero -> result = 0
// TC-10 Max normal × max normal -> tests overflow path
// TC-11 Denormal inputs (exp=0) -> subnormal product check
// TC-12 Two-pair cancellation -> a=-b, result should be 0
//
// 1000 LFSR pseudo-random vectors:
// Seed: 16'hBEEF (deterministic, not $random)
// Oracle: reference gf16_dot4 instance (instantiated inline)
// Falsification: any DUT mismatch → FAIL + $display details
//
// R-SI-1 compliance: ZERO '*' in synthesisable RTL.
// The oracle uses a reference instantiation of gf16_dot4 (which
// itself uses gf16_mul containing the legacy '*' — acceptable in
// testbench oracle only, NOT in the DUT under test).
//
// R-SI-9 R7 FALSIFIER:
// Task `check` asserts DUT result === oracle result.
// Any bit-level deviation triggers fail_count increment and
// $display FAIL message — catches any deviation from the
// golden XOR-popcount oracle.
//
// R-SI-8 R5 HONEST:
// Testbench is STATIC — not run in sandbox (no iverilog in CI).
// Compile command:
// iverilog -g2012 -o sim_tb_gf16_dot4_wallace.vvp \
// sim/tb_gf16_dot4_wallace.v \
// src/gf16_dot4_wallace.v \
// src/gf16_dot4.v \
// src/gf16_mul.v \
// src/gf16_add.v
// vvp sim_tb_gf16_dot4_wallace.vvp
//
// AUTHOR: Vasilev Dmitrii <admin@t27.ai>
//
// phi^2 + phi^-2 = 3 · Wave-24 RVR-017 dry-run · DOI 10.5281/zenodo.19227877
// ============================================================

`default_nettype none
`timescale 1ns / 1ps

module tb_gf16_dot4_wallace;

// ---- DUT wiring ----
reg [15:0] a0, a1, a2, a3;
reg [15:0] b0, b1, b2, b3;
wire [15:0] dut_result;
wire [15:0] ref_result;

// DUT: Wallace-tree implementation under test
gf16_dot4_wallace dut (
.a0(a0), .a1(a1), .a2(a2), .a3(a3),
.b0(b0), .b1(b1), .b2(b2), .b3(b3),
.result(dut_result)
);

// Reference oracle: baseline gf16_dot4 (golden truth)
// R-SI-9: any deviation from oracle => FAIL (falsification witness)
gf16_dot4 ref (
.a0(a0), .a1(a1), .a2(a2), .a3(a3),
.b0(b0), .b1(b1), .b2(b2), .b3(b3),
.result(ref_result)
);

// ---- Counters ----
integer pass_count, fail_count, vec_idx;

// ---- GoldenFloat-16 constants ----
// Format: [15]=sign, [14:9]=exp (bias=31), [8:0]=mant (hidden bit)
localparam GF16_ZERO = 16'h0000; // 0.0
localparam GF16_NEG_ZERO = 16'h8000; // -0.0
localparam GF16_ONE = 16'h3E00; // 1.0 (exp=31, mant=0)
localparam GF16_NEG_ONE = 16'hBE00; // -1.0
localparam GF16_TWO = 16'h4000; // 2.0 (exp=32, mant=0)
localparam GF16_FOUR = 16'h4200; // 4.0 (exp=33, mant=0)
localparam GF16_INF_POS = 16'h7E00; // +Inf
localparam GF16_INF_NEG = 16'hFE00; // -Inf
localparam GF16_NAN = 16'hFE01; // NaN
// phi-derived sentinel: 0x47C0
// exp=35, mant=9'h1C0 = 9'b111000000 -> value approx 1.875 * 2^4 = 30.0
// R-SI-7 trace: phi^2 ≈ 2.618; 0x47C0 chosen as phi-structured
// test vector per Issue #4 Change C acceptance sentinel list
localparam GF16_PHI_SEN = 16'h47C0;
// Max normal: exp=62 (0x3E), mant=all-ones (0x1FF)
localparam GF16_MAX_NRM = 16'h7DFF; // largest finite positive
// Small denormal: exp=0, mant=1
localparam GF16_DENORM = 16'h0001;

// ---- LFSR state (16-bit Fibonacci, taps 16,14,13,11 = x^16+x^14+x^13+x^11+1) ----
reg [15:0] lfsr;

task lfsr_next;
begin
// Galois LFSR: taps at bits 16,14,13,11 -> poly 0xD008
// Verified: period = 65535 (maximal-length 16-bit LFSR)
lfsr = {lfsr[14:0], lfsr[15] ^ lfsr[13] ^ lfsr[12] ^ lfsr[10]};
end
endtask

// ---- Check task: compare DUT vs oracle ----
// R-SI-9: this task IS the falsification witness.
// Any result deviation triggers FAIL — catches all RTL bugs.
task automatic check;
input [127:0] name; // up to 16 ASCII chars packed
begin
#1; // allow combinational settle
if (dut_result === ref_result) begin
pass_count = pass_count + 1;
$display("PASS [%s] a0=%h a1=%h a2=%h a3=%h b0=%h b1=%h b2=%h b3=%h result=%h",
name, a0, a1, a2, a3, b0, b1, b2, b3, dut_result);
end else begin
fail_count = fail_count + 1;
$display("FAIL [%s] a0=%h a1=%h a2=%h a3=%h b0=%h b1=%h b2=%h b3=%h dut=%h ref=%h",
name, a0, a1, a2, a3, b0, b1, b2, b3, dut_result, ref_result);
end
end
endtask

// ---- LFSR random check (no name) ----
task automatic check_rand;
begin
#1;
if (dut_result === ref_result) begin
pass_count = pass_count + 1;
end else begin
fail_count = fail_count + 1;
$display("FAIL [RAND vec=%0d] a0=%h a1=%h a2=%h a3=%h b0=%h b1=%h b2=%h b3=%h dut=%h ref=%h",
vec_idx, a0, a1, a2, a3, b0, b1, b2, b3, dut_result, ref_result);
end
end
endtask

// ====================================================================
// Main test body
// ====================================================================
initial begin
pass_count = 0;
fail_count = 0;
lfsr = 16'hBEEF; // deterministic seed — R-SI-7 trace: 0xBEEF = 48879

// ----------------------------------------------------------------
// TC-01: All-zero inputs
// a_i = 0, b_i = 0 for all i -> result = 0.0
// ----------------------------------------------------------------
a0 = GF16_ZERO; a1 = GF16_ZERO; a2 = GF16_ZERO; a3 = GF16_ZERO;
b0 = GF16_ZERO; b1 = GF16_ZERO; b2 = GF16_ZERO; b3 = GF16_ZERO;
check("TC-01 all0 ");

// ----------------------------------------------------------------
// TC-02: All-positive unit inputs
// a_i = 1.0, b_i = 1.0 for all i -> each product = 1.0
// sum = 4.0
// ----------------------------------------------------------------
a0 = GF16_ONE; a1 = GF16_ONE; a2 = GF16_ONE; a3 = GF16_ONE;
b0 = GF16_ONE; b1 = GF16_ONE; b2 = GF16_ONE; b3 = GF16_ONE;
check("TC-02 4x1.0 ");

// ----------------------------------------------------------------
// TC-03: All-negative mantissa
// a_i = -1.0, b_i = -1.0 -> product = +1.0 each
// sum = +4.0 (same as TC-02 by sign rules)
// ----------------------------------------------------------------
a0 = GF16_NEG_ONE; a1 = GF16_NEG_ONE; a2 = GF16_NEG_ONE; a3 = GF16_NEG_ONE;
b0 = GF16_NEG_ONE; b1 = GF16_NEG_ONE; b2 = GF16_NEG_ONE; b3 = GF16_NEG_ONE;
check("TC-03 4xn1 ");

// ----------------------------------------------------------------
// TC-04: Alternating signs (cancellation)
// products: +1.0, -1.0, +1.0, -1.0 -> sum = 0.0
// ----------------------------------------------------------------
a0 = GF16_ONE; a1 = GF16_NEG_ONE; a2 = GF16_ONE; a3 = GF16_NEG_ONE;
b0 = GF16_ONE; b1 = GF16_ONE; b2 = GF16_ONE; b3 = GF16_ONE;
check("TC-04 alt+- ");

// ----------------------------------------------------------------
// TC-05: phi-derived sentinel pair 0x47C0
// R-SI-7 trace: phi^2 ≈ 2.618 encoded ~0x47C0 area
// Tests non-trivial mantissa patterns
// ----------------------------------------------------------------
a0 = GF16_PHI_SEN; a1 = GF16_PHI_SEN; a2 = GF16_PHI_SEN; a3 = GF16_PHI_SEN;
b0 = GF16_ONE; b1 = GF16_ONE; b2 = GF16_ONE; b3 = GF16_ONE;
check("TC-05 phi4x ");

// ----------------------------------------------------------------
// TC-06: Sentinel pairs alternating 1.0 and -1.0 on both a and b
// a = (1.0, -1.0, 1.0, -1.0), b = (1.0, -1.0, 1.0, -1.0)
// products: 1.0, 1.0, 1.0, 1.0 -> sum = 4.0
// (negative * negative = positive)
// ----------------------------------------------------------------
a0 = GF16_ONE; a1 = GF16_NEG_ONE; a2 = GF16_ONE; a3 = GF16_NEG_ONE;
b0 = GF16_ONE; b1 = GF16_NEG_ONE; b2 = GF16_ONE; b3 = GF16_NEG_ONE;
check("TC-06 snt ");

// ----------------------------------------------------------------
// TC-07: All +Inf inputs
// Inf * Inf = +Inf; Inf + Inf = +Inf
// ----------------------------------------------------------------
a0 = GF16_INF_POS; a1 = GF16_INF_POS; a2 = GF16_INF_POS; a3 = GF16_INF_POS;
b0 = GF16_INF_POS; b1 = GF16_INF_POS; b2 = GF16_INF_POS; b3 = GF16_INF_POS;
check("TC-07 +Inf ");

// ----------------------------------------------------------------
// TC-08: Mixed Inf and NaN
// a0=+Inf, b0=NaN -> first product = NaN; result should be NaN
// ----------------------------------------------------------------
a0 = GF16_INF_POS; a1 = GF16_ONE; a2 = GF16_ONE; a3 = GF16_ONE;
b0 = GF16_NAN; b1 = GF16_ONE; b2 = GF16_ONE; b3 = GF16_ONE;
check("TC-08 NaN ");

// ----------------------------------------------------------------
// TC-09: Zero dot non-zero
// a_i = 0, b_i = max_normal -> all products = 0; sum = 0
// ----------------------------------------------------------------
a0 = GF16_ZERO; a1 = GF16_ZERO; a2 = GF16_ZERO; a3 = GF16_ZERO;
b0 = GF16_MAX_NRM; b1 = GF16_MAX_NRM; b2 = GF16_MAX_NRM; b3 = GF16_MAX_NRM;
check("TC-09 0*max ");

// ----------------------------------------------------------------
// TC-10: Max normal times max normal (overflow test)
// Each product may overflow to +Inf depending on gf16_mul
// ----------------------------------------------------------------
a0 = GF16_MAX_NRM; a1 = GF16_MAX_NRM; a2 = GF16_MAX_NRM; a3 = GF16_MAX_NRM;
b0 = GF16_MAX_NRM; b1 = GF16_MAX_NRM; b2 = GF16_MAX_NRM; b3 = GF16_MAX_NRM;
check("TC-10 max^2 ");

// ----------------------------------------------------------------
// TC-11: Denormal inputs (exp=0, mant=1 — subnormal)
// Product of two denormals is typically 0 in GoldenFloat-16
// ----------------------------------------------------------------
a0 = GF16_DENORM; a1 = GF16_DENORM; a2 = GF16_DENORM; a3 = GF16_DENORM;
b0 = GF16_DENORM; b1 = GF16_DENORM; b2 = GF16_DENORM; b3 = GF16_DENORM;
check("TC-11 denorm");

// ----------------------------------------------------------------
// TC-12: Two-pair cancellation
// a0=1, b0=phi_sen; a1=1, b1=phi_sen;
// a2=phi_sen, b2=-1; a3=phi_sen, b3=-1
// -> phi_sen + phi_sen - phi_sen - phi_sen = 0 (if add is exact)
// ----------------------------------------------------------------
a0 = GF16_ONE; a1 = GF16_ONE;
a2 = GF16_PHI_SEN; a3 = GF16_PHI_SEN;
b0 = GF16_PHI_SEN; b1 = GF16_PHI_SEN;
b2 = GF16_NEG_ONE; b3 = GF16_NEG_ONE;
check("TC-12 cancel");

$display("");
$display("--- Corner cases complete: %0d PASS, %0d FAIL ---", pass_count, fail_count);
$display("");

// ================================================================
// 1000 LFSR pseudo-random vectors
// Compare DUT vs reference gf16_dot4 oracle on every vector.
// R-SI-9: falsification witness — any mismatch = FAIL
// ================================================================
for (vec_idx = 0; vec_idx < 1000; vec_idx = vec_idx + 1) begin
// Advance LFSR 8 times to generate 8 × 16-bit values
lfsr_next; a0 = lfsr;
lfsr_next; a1 = lfsr;
lfsr_next; a2 = lfsr;
lfsr_next; a3 = lfsr;
lfsr_next; b0 = lfsr;
lfsr_next; b1 = lfsr;
lfsr_next; b2 = lfsr;
lfsr_next; b3 = lfsr;
check_rand;
end

// ================================================================
// Summary
// ================================================================
$display("");
$display("=== tb_gf16_dot4_wallace SUMMARY ===");
$display("PASS: %0d", pass_count);
$display("FAIL: %0d", fail_count);
$display("TOTAL: %0d", pass_count + fail_count);
if (fail_count == 0)
$display("VERDICT: PASS -- gf16_dot4_wallace matches reference oracle on all %0d vectors",
pass_count + fail_count);
else
$display("VERDICT: FAIL -- %0d mismatch(es) detected", fail_count);
$display("Anchor: phi^2 + phi^-2 = 3 DOI:10.5281/zenodo.19227877");
$finish;
end

endmodule
// phi^2 + phi^-2 = 3 · Wave-24 RVR-017 dry-run · DOI 10.5281/zenodo.19227877
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