fix: Lane L 4609-fanout split — unblocks PR #46 GDS

[gHashTag]

Problem

Net u_mm16.gen_row[0].gen_col[0].u_pc.s1_same[0] has 4,609 fanout terminals in the 16×16 GF16 matmul, causing setup violations at TT corner 25C/1.80V under 20 ns clock (50 MHz). This blocks PR #46 from reaching GDS.

Root Cause

In vsa_matmul_16x16, the single pipe_valid_in reg drove all 256 valid_in ports simultaneously. Inside each gf16_popcount16 instance, s1_same[15:0] was a monolithic 16-bit register with bits fanning out across the full 8-pair adder tree, creating the observed 4609-net load at synthesis.

Fix

vsa_matmul_16x16.v

• Added reg [15:0] pipe_valid_row — 16 registered copies of pipe_valid_in, one per row.
• Each pipe_valid_row[gi] drives exactly 16 PC units (one row), reducing fanout from 4609 → ≤16 per driver.

gf16_popcount16.v

• Split reg [15:0] s1_same → reg [7:0] s1_same_lo + reg [7:0] s1_same_hi (two separate register banks).
• Split reg [15:0] s1_diff → reg [7:0] s1_diff_lo + reg [7:0] s1_diff_hi similarly.
• Each bank feeds only its 4-pair half of the Stage-2 adder tree (~4 loads/bit vs. the original full-tree exposure).

Compliance

• Pure Verilog-2005: no logic, one reg per line.
• R-SI-1: zero * operators.
• LATENCY=3 pipeline depth and functional behaviour unchanged.

Anchor

φ²+φ⁻²=3 · DOI 10.5281/zenodo.19227877 · Apache-2.0

Closes / unblocks #46

[gHashTag]

Superseded by PR #47 (clock relax 25ns) which won the Lane L CI race — finishing 88 seconds earlier. Both passed all 4 GDS checks; #47 chosen by race protocol. Closing.