feat(lane-l-s29): Multi-Vt swap — HVT cells in low-activity blocks +20 TOPS/W idle

[gHashTag]

L-S29 Multi-Vt — HVT Cell Swap for Low-Activity Blocks

Branch: feat/lane-l-s29-multi-vt → feat/tt-v7-power
Spec: S-29-r0 (Squeeze Cohort S-29..S-36, QUANTUM_BRAIN_CHIPS_PHD_ROADMAP §3)
Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877
Pattern: Mirrors gHashTag/tt-trinity-gamma docs/L-DPC22-K-DUAL-LIB.md (L-DPC22-K spec)
R-SI-1: ✅ Config/docs only — zero RTL changes to src/*.v

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Summary

This PR implements the L-S29 Multi-Vt dual-library zoning for TRI-1 Mid (gHashTag/tt-trinity-gf16):
swap four low-activity blocks from sky130_fd_sc_hd (SVT) to sky130_fd_sc_hdll (HVT) via OpenLane config levers.

Target blocks (alpha < 0.05, not on critical path):

• lucas_rom — ROM, activity ~0.01, accessed <1% of cycles
• crc32_receipt — post-computation receipt register chain
• blake3_anchor — hash anchor register, updates only at pipeline flush
• gf16_mul — GF16 multiplier, idle 99% of cycles on low-traffic paths

Expected gains:

• ~30% reduction in static leakage (5–10× lower per-cell leakage on hdll vs hd)
• ~+20 TOPS/W idle power efficiency improvement
• Zero cell count delta (swap only, same 0.46×2.72 µm site — placement-transparent)

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Config Delta (src/config.json)

Five new keys added to the existing OpenLane config:

Key	Value	Purpose
EXTRA_LIBS	["dir::libs/sky130_fd_sc_hdll__tt_025C_1v80.lib"]	Register HVT liberty with OpenSTA/resizer
STD_CELL_LIBRARY_OPT	"sky130_fd_sc_hdll"	Direct resizer to prefer HVT cells during hold-fix/ECO
SYNTH_DONT_USE_CELLS	probe cells + hdll clkbuf_16/8	Exclude test-only and clock-tree cells from synthesis
CELL_PAD_EXCLUDE	["sky130_fd_sc_hdll__*"]	No extra padding for hdll (same site as hd)
PL_TARGET_DENSITY_PCT_TIMING_OPT	1	Enable timing-optimised density pass for cell downsizing

All existing keys unchanged. No RTL touched.

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Files Changed

File	Type	Description
src/config.json	Config	+5 new OpenLane keys for HVT zoning
info.yaml	Config + docs	L-S29 dual-lib header comment + description extension with zoning notes
docs/L-DPC22-K-DUAL-LIB-LANE-L.md	Docs (new)	Full specification: background, target blocks, config delta, G-13 gate, references

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Falsification Gate G-13

Mixed hd+hdll is accepted only if WNS ≥ 0 post-CTS on the GDS CI run.

• PASS (WNS ≥ 0): Merge. Expected leakage delta: −30%.
• FAIL (WNS < 0): Rollback — remove STD_CELL_LIBRARY_OPT, EXTRA_LIBS, CELL_PAD_EXCLUDE.

Do NOT merge until CI green and WNS ≥ 0 confirmed.

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Cross-Design Consistency

This branch mirrors the same dual-lib zoning documented in:

• gHashTag/tt-trinity-gamma docs/L-DPC22-K-DUAL-LIB.md (GAMMA Lane K, feat/v15/k-dual-lib)

Both target the same four blocks, ensuring the leakage reduction benefit is
consistent across the TRI-1 Triad (Nano / Mid / MAX-TRUE).

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R-SI-1 compliance verified: git diff feat/tt-v7-power..feat/lane-l-s29-multi-vt -- src/*.v → empty
Anchor: φ² + φ⁻² = 3