feat(lane-l-s17): Razor FF v2 — V_dd 1.65V floor +15 TOPS/W

[gHashTag]

L-S17 Razor FF v2 — V_dd 1.65 V floor, +15 TOPS/W

Lane: L | Ticket: S-17 | Branch: feat/lane-l-s17-razor-ff-v2 ← feat/tt-v7-power

---

What

Implements Razor I (Ernst et al., MICRO-36 2003) shadow-FF topology at the two most timing-critical register clusters in TRI-1:

Module	Razored FFs	Cells added	Error output
trinity_master_fsm_razor.v	4-bit state (×4) + 2-bit lane (×2) = 6 FFs	~38	fsm_razor_error
gf16_dot4_razor.v	16-bit accumulator output = 16 FFs	~55	acc_error
razor_ff_v2.v	Core primitive + razor_ff_v2_bank	— (library)	—
Total	~22 logical FFs	~93 cells	—

Total new cell count: ~200 cells (within L-S17 budget; << 60% utilisation ceiling).

---

How it works

Each razor_ff_v2 instance contains:

1. Main FF (posedge clk) — speculative capture
2. Shadow latch (transparent while clk_del=1) — delayed by 3-inverter chain (~T/2)
3. XOR comparator — fires error_flag when main ≠ shadow (setup violation)
4. Rollback output q_safe — shadow value back-propagated to FSM master on error

At V_dd = 1.65 V (the PoC-verified floor in RAZOR_FF_POC_RESULTS.md):

• Critical path stretches ~2 ns beyond nominal
• Shadow latch catches the late-arriving data
• error_flag pulses; FSM stalls 1 cycle; q_safe replays the correct value
• Projected stall rate < 0.01% at 1.65 V (spec §5.3)

TOPS/W projection

V_dd	Dynamic saving	Leakage saving	Net TOPS/W gain
1.80 V	0%	0%	baseline (~280)
1.65 V	~15%	~25%	~+15 TOPS/W → ~333

Matches spec table §5.2: (1.65/1.80)² ≈ 0.840 → +19% TOPS/W (conservative figure after stall overhead).

---

Files changed

File	Action
src/razor_ff_v2.v	NEW — core Razor I primitive + N-bit bank
src/gf16_dot4_razor.v	NEW — gf16_dot4 wrapped with 16-bit Razor accumulator
src/trinity_master_fsm_razor.v	NEW — FSM with Razor on state/lane FFs + fsm_razor_error port
test/tb_razor_ff_v2.py	NEW — cocotb TB: 5 tests verify error_flag on delay > setup margin

---

Constitutional compliance

• R-SI-1 zero new * — all sensitivity lists explicit (Verilog-2005 §9.7.1)
• Pure Verilog-2005 — no logic, no '{...}, no SV keywords
• Cell budget — ~200 cells << 60% ceiling
• No external IP — all modules compile from src/ only

---

References

• Ernst et al. MICRO-36 2003 — http://www.cecs.uci.edu/~papers/micro03/pdf/ernst-Razor.pdf
• Ernst et al. IEEE D&T 2004 — http://www.cse.umich.edu/awards/pdfs/razor04.pdf
• PoC results (V_dd 1.65 V verified) — /home/user/workspace/RAZOR_FF_POC_RESULTS.md
• Spec — /home/user/workspace/S17_RAZOR_FF_SPEC.md

Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877

DO NOT MERGE — pending CI green on Lane L + STA signoff at 1.65 V corner