feat(lane-l-z02): operand isolation — +8 TOPS/W via toggle suppression

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L-Z02 Operand Isolation (Data Gating)

AND-gate operand bus inputs to unused functional units. Prevents toggle activity propagation into idle blocks. Saves ~8% dynamic power → +8 TOPS/W.

Design Intent

• Each functional unit (gf16_mul lanes, gf16_add, gf16_dot4/dot8, alu9_decoder) gets an operand_iso_en signal from the tile FSM
• Operand register outputs AND-ed with enable before reaching the unit
• When enable=0 → operand inputs see all-zero → zero toggle activity downstream

Files Changed

File	Change
src/operand_iso_buf.v	NEW — Parameterized N-bit operand isolator: assign out = {N{enable}} & in;
src/trinity_gf16_tile.v	16 operand_iso_buf instances (a0..a7, b0..b7), operand_iso_en from FSM
src/trinity_mesh_2x2.v	L-Z02 comment block documenting mesh-level isolation
src/tt_um_ghtag_trinity_gf16.v	8-bit isolator on alu9_decoder inputs (enable=post_done)
sim/tb_l_z02_operand_iso.v	NEW — 6-test toggle-count verification testbench
info.yaml	Added operand_iso_buf.v to source_files

Enable Signal Logic

• Trinity tiles: operand_iso_en register, initialized 0 (isolated) at reset. Set on first LOAD_A packet (tile armed). Tiles that never receive a load packet propagate all-zero operands permanently.
• alu9_decoder: enable = post_done — decoder inputs isolated during reset/POST phase.

Cell Budget

Path	Instances	Bits	AND2 cells
Tile a0..a3 (dot4)	4	16	64
Tile b0..b3 (dot4)	4	16	64
Tile a4..a7 (dot8 upper)	4	16	64
Tile b4..b7 (dot8 upper)	4	16	64
alu9_decoder	1	8	8
4 tiles total			4 × 256 + 8 = 1032

~1032 sky130_fd_sc_hd__and2_1 cells. Well within budget.

Verification

All 6 tests pass under iverilog -g2005:

• T1a/T1b: enable=0 → out=0x0000 for any input
• T2a/T2b: enable=1 → transparent pass-through (GF16 1.0, 30.0)
• T3: enable=0 → 0 toggles across 100 LFSR random vectors
• T4: enable=1 → 100 toggles across same vectors

Constitutional Compliance

• R-SI-1: zero * operators in all new/modified code
• Pure Verilog-2005: no SystemVerilog constructs
• No external IP added

Projected Gain

8% dynamic power reduction per tile → **+8 TOPS/W** system-wide.

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Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877