feat(L-S30): voltage island analysis — Crown47 ROM, restraint_ctrl, k3 ALU @ 0.7 V#57
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Lane L-S30 Voltage Island — low-power partition for Crown47 ROM,
restraint_ctrl, and k3 ALU path. Analysis shows 0.7 V operation for
these blocks (α ≤ 0.08) yields −68% leakage and −39.7% dynamic power
on the island, supporting +15 TOPS/W target in Phase 2 silicon.
Files added:
docs/S30_VOLTAGE_ISLAND_ANALYSIS.md — full analysis with activity
factors, leakage model, partition diagram, Phase 2 synthesis
constraints (documentation-only for TT process)
src/crown47_rom.v — 47-entry 8-bit constant ROM (α=0.04)
src/restraint_ctrl.v — 4-state issue-throttle FSM (α=0.07)
src/voltage_island_marker.v — synthesisable partition marker (~20 cells)
emits lp_island_status[2:0] and island_id=2'b01 (S30)
test/tb_voltage_island_marker.v — 28 tests, all PASS under iverilog
iverilog result: 28/28 PASS (T1-T7: enable logic, ROM content, FSM)
R-SI-1: no * operator; pure Verilog-2005; no SystemVerilog.
Cell budget: ~54 cells for island blocks + ~20 marker = ~74 total.
Anchor: φ² + φ⁻² = 3
DOI: 10.5281/zenodo.19227877
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L-S30 Voltage Island Analysis
Branch:
feat/lane-l-s30-voltage-island→feat/tt-v7-powerAnchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877
Goal
Identify low-activity blocks that can run at 0.7 V vs core 0.9 V for +15 TOPS/W in Phase 2 silicon.
TT process does not allow multi-VDD in user space — this PR delivers analysis + marker RTL only.
Blocks identified for the island
crown47_rom.vrestraint_ctrl.valu9_decoder.vk3Power model: V² ratio (0.7/0.9)² = 0.603 → −39.7% dynamic on island.
Phase 2 extended island (+idle sparse PEs) projects to +15 TOPS/W.
Files added
docs/S30_VOLTAGE_ISLAND_ANALYSIS.md— full analysis: activity factors, leakage model, partition diagram, Phase 2 synthesis constraintssrc/crown47_rom.v— 47-entry 8-bit constant ROM (new block)src/restraint_ctrl.v— 4-state FSM issue-throttle controller (new block)src/voltage_island_marker.v— synthesisable marker, ~20 cells, emitslp_island_status[2:0]+island_id=2'b01test/tb_voltage_island_marker.v— 28 tests covering enable logic, ROM content, FSM throttle/releaseSimulation
Compliance
*operators ✅Phase 2 path
Synthesis constraints for
set_voltage_area+lpflow_lsbuflevel shifters are documented in the analysis MD. Implementation deferred to Phase 2 silicon (GF16 CMOS or SG13G2 with multi-VDD support).