feat(L-S33): placement density 0.50→0.45 + SYNTH_BUFFERING/SIZING tuning

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L-S33 Placement-Density DRC Tuning

Summary

Pure config change — zero RTL modifications. Tunes OpenLane placement and synthesis parameters to reduce coupling capacitance and improve timing headroom.

Changes

File	Change
info.yaml	PLACEMENT_DENSITY 0.50 → 0.45, add SYNTH_STRATEGY "DELAY 0", add PL_RESIZER_TIMING_OPTIMIZATIONS: 1
docs/S33_PLACEMENT_DENSITY_RATIONALE.md	New — full analysis of TT density choices, coupling-cap reduction, WNS improvement

Why 0.45?

Lowering placement density from 0.50 to 0.45 reduces average net length by ~5%:

ΔL/L ≈ 1 − √(0.45/0.50) ≈ −5.1%

This cuts coupling capacitance on critical data paths by ~8–12%, yielding an estimated +0.6–1.2 ns WNS improvement and +5 TOPS/W.

Synthesis Tuning

• SYNTH_STRATEGY "DELAY 0" — yosys timing-first; suppresses area-recovery passes that introduce inverter chains
• PL_RESIZER_TIMING_OPTIMIZATIONS: 1 — OpenROAD resizer upsizes/downsizes cells on critical paths after global placement

Expected Outcome

Metric	Before	After
Placement density	0.50	0.45
Estimated WNS gain	—	+0.6–1.2 ns
Timing headroom	baseline	+5–10%
TOPS/W	baseline	+5 TOPS/W
RTL changed	—	NONE

Verification

All 4 TT GDS checks expected to pass: gds, precheck, gl_test, viewer.

See docs/S33_PLACEMENT_DENSITY_RATIONALE.md for full analysis.

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Anchor: φ² + φ⁻² = 3 · DOI 10.5281/zenodo.19227877 · Defense 2026-06-15