WIP: Merges for documentation and to support LIFCL 33/33U by jdavidberger · Pull Request #49 · gatecat/prjoxide

jdavidberger · 2026-01-28T14:56:35Z

The changes here are related to:

Updated documentation
Support for adding new platform types in general
Support for platforms LIFCL 33/33U
Somewhat faster fuzzing -- mostly by cacheing more things

- Added support for related BELs - Added support to parse compressed bitstreams - Support new device attributes - Support serializing deltas for checkpoint / debugging

…tas; refactor logic for tiletypes which configure adjacent tiles

…nd improved UI

… routing

docs/bels/overview.md

docs/general/cacheing.md

gatecat · 2026-01-28T16:11:17Z

docs/database.md

+This serves as a master listing of each device and metadata associated with that device:
+
+- packages: Comes from various lattice documentation, can also be seen by looking at the radiant device selection dialog.
+- frame metadata: There are various necessary peices of data here. All are available in the "sysCONFIG Guide for Nexus Platform" document from the lattice website.


might be nice to expand this a bit more?

fuzzers/LFCPNX/shared/empty_40.v

gatecat · 2026-01-28T16:13:55Z

fuzzers/LIFCL/001-plc-routing/fuzzer.py


-cfg = FuzzConfig(job="PLCROUTE", device="LIFCL-40", sv="../shared/route_40.v", tiles=["R16C22:PLC"])
+def run_cfg(device):
+    tile = list(tiles.get_tiles_by_tiletype(device, "PLC").keys())[0]


there was a degree of caution not to pick a tile too close to the edge of the device because that could falsely cause some extra edge routing to be included, have you checked this?

gatecat · 2026-01-28T16:37:40Z

libprjoxide/prjoxide/src/bels.rs

+                "PIOA.SEIO18.BASE_TYPE" => vec![Bel::make_seio18(0)],
+                "PIOB.SEIO18.BASE_TYPE" => vec![Bel::make_seio18(1)],
+                "PIOA.DIFFIO18.BASE_TYPE" => vec![Bel::make_diffio18()],
+                "PIOB.DIFFIO18.BASE_TYPE" => vec![Bel::make_diffio18()],


I don't think PIOB.DIFFIO18 should ever happen?

I don't think so either, will remove

gatecat · 2026-01-28T16:38:36Z

libprjoxide/prjoxide/src/bitstream.rs

            if in_metadata && self.check_preamble(&COMMENT_END) {
                if curr_meta.len() > 0 {
                    self.metadata.push(curr_meta.to_string());
+ 		    if curr_meta.is_ascii() {


looks like spaces and tabs got mixed here?

tools/extract_tilegrid.py

util/fuzz/primitives.py

gatecat · 2026-01-28T17:00:57Z

util/fuzz/primitives.py

+    PinSetting(name="ENCLKOS4", dir="in", desc="Enable E output (CLKOS4). Active high. PLL CIB input.", bits=None),
+    PinSetting(name="ENCLKOS5", dir="in", desc="Enable F output (CLKOS5). Active high. PLL CIB input.", bits=None),
+    PinSetting(name="FBKCK", dir="in", desc="", bits=None),
+    PinSetting(name="LEGACY", dir="in", desc="PLL legacy mode signal. Active high to enter the mode. Enabled by lmmi_legacy fuse. PLL CIB input.", bits=None),


I think we shouldn't scrape descriptions from the lattice html unfortunately. It creates a theoretical copyright issue (as this is text rather than just a raw fact about an FPGA) particularly when they often reference weird lattice internal things, even if they're public facing docs.

I've removed the ones from the primitives.py file, but made it so definitions that get scraped in from the web docs have the lattice descriptions. Not sure if this is good enough or not; easy enough to keep them out altogether if needed though

…t of introspective features using the full node db

… to different api calls

… changes

…for merge/commit into db

jdavidberger · 2026-02-19T07:02:50Z

I increased the scope by a decent margin; I added overlays and a general purpose pip solver. Probably the big thing now is making sure the overlays / 000 fuzzer make sense and are documented well enough.

gatecat

in general looking good, had another glance at this with a few more comments. let me know if anything else is waiting on me!

gatecat · 2026-02-25T07:05:33Z

docs/database.md

+
+### iptypes
+
+These files are generated by various fuzzers associated with the given primitive. They map out the relationship between configuration parameters and the bits set in the bitstream.


maybe add a note that these specifically relate to configuration in the "IP space" (baseaddrs.json) rather than the main CRAM grid?

gatecat · 2026-02-25T07:07:07Z

fuzzers/LIFCL/031-io_mode/fuzzer.py

+    return list(configs.values())
+
+configs = create_device_configs("LIFCL-33") + create_device_configs("LIFCL-33U") + create_device_configs("LIFCL-17") + create_device_configs("LIFCL-40")
+#           [


we can probably just remove this - it will always be in the git history if it needs fishing out again

gatecat · 2026-02-25T07:08:10Z

fuzzers/LIFCL/050-cib-special/fuzzer.py

-                    lambda x: dict(arcs_attr=arcs_attr) if x == "YES" else {}, False)
+                    lambda x: dict(arcs_attr=arcs_attr) if x == "YES" else {}, False, executor=executor)

-        # CIBMUXIN -> CIBMUXOUT


was there a specific reason for removing this?

gatecat · 2026-02-25T07:12:08Z

fuzzers/LIFCL/unused/001-plc-routing/fuzzer.py

probably instead of moving to unused/ just get rid of this? again it will be around in the git history if needed

gatecat · 2026-02-25T07:14:05Z

libprjoxide/prjoxide/src/bitstream.rs

-                    println!("done");
+                    debug!("done");
                }
+                LSC_READ_DR_UES => {


purely out of interest, when is radiant including this command in a bitstream?

gatecat · 2026-02-25T07:15:39Z

libprjoxide/prjoxide/src/database.rs

    pub always_on: BTreeSet<ConfigBit>,
+    #[serde(default)]
+
+    // Tiletype and relative offset for the tiles that this tiletype configures -- that is, changes in


I don't think this comment is quite correct - it seems to just be a relative offset and not a tiletype?

gatecat · 2026-02-25T07:19:34Z

util/common/tiles.py

+
+        tiles_at_rc = get_owning_tiles_for_rc(rc)
+
+        tileless_rcs = set(["R37C52_H01E0100", "R73C160_JIVREFI4_IVREF_CORE"])


maybe this should be gated on LIFCL-33[U]? R37C52_H01E0100 could plausibly exist in other devices too and not be weird I think?

jdavidberger added 19 commits January 5, 2026 22:33

Document some of how the database is laid out

8faaa3a

Update scripting for 2023-2025 radiant

6e60732

Add bel overview

4e3472d

Add docs

54656f3

Changes to prjoxide to support lifcl-33 devices.

dddc797

- Added support for related BELs - Added support to parse compressed bitstreams - Support new device attributes - Support serializing deltas for checkpoint / debugging

Changes related to bringing support for lifcl-33 devices

b8de947

Changes around IO for lifcl-33

5e3c9c5

Fix undriven signal warning

daae938

Remove debug code

9393828

Add support for some 33u

80e9a27

Fix 110

853b293

Incorporate env logger and py logger. Add more methods for adding del…

d6b924f

…tas; refactor logic for tiletypes which configure adjacent tiles

Gitignore / docs

39d0398

Add node database, add futures / async support, misc util functions a…

08f9b43

…nd improved UI

Make sure to print error and exit with error code if an error exists

387f835

Updated fuzzers; add support for 33u OSCD, improved general tile/site…

75cf8b6

… routing

Fix borrow issues with db; docs

ace51a1

Docs; examples

1926dd0

Merge in upstream

eedca4a

jdavidberger changed the title ~~Merges for documentation and to support LIFCL 33/33U~~ WIP: Merges for documentation and to support LIFCL 33/33U Jan 28, 2026

gatecat reviewed Jan 28, 2026

View reviewed changes

jdavidberger added 9 commits February 13, 2026 11:02

Add overlays, reformat, and 33 handling to libprjoxide

32449e3

Enabling chnages to node db and tiles, other places. General build ou…

555f78b

…t of introspective features using the full node db

Reorg to use the standard pip/overlay generator

51627ce

Commit before refactor

dd4f81b

Update to use status line, fix some incorrectly bound lambdas, update…

27de320

… to different api calls

Move interconnect fuzzers to unused dir

40c9685

Changes to get fuzzers to work with new api; overlay and rel location…

1ecd2d8

… changes

Incorporating database changes from $dir

a9d65f1

Web parsing code; clean up which primitives we import. Add scripting …

66ecd69

…for merge/commit into db

Incorporate feedback; add docs; general cleanup

2457dc1

Fix overlay naming, make work for other family

b10f4eb

gatecat reviewed Feb 25, 2026

View reviewed changes


		### iptypes

		These files are generated by various fuzzers associated with the given primitive. They map out the relationship between configuration parameters and the bits set in the bitstream.


		tiles_at_rc = get_owning_tiles_for_rc(rc)

		tileless_rcs = set(["R37C52_H01E0100", "R73C160_JIVREFI4_IVREF_CORE"])

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jdavidberger commented Jan 28, 2026

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jdavidberger commented Feb 19, 2026

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