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[RVV] Add missing maxpool and avgpool rvv kernels #9622

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[RVV] Add missing maxpool and avgpool rvv kernels #9622

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7596bbc
rvv maxpool for f32, f16, s8, u8
ken-unger Mar 2, 2026
afaabc2
cleanup rvv maxpool, add rvv avgpool
ken-unger Mar 3, 2026
81b1ddb
merge maxpool-rvv from latest master
ken-unger Mar 29, 2026
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4 changes: 3 additions & 1 deletion cmake/gen/rvv_microkernels.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@

SET(PROD_RVV_MICROKERNEL_SRCS
src/f32-argmaxpool/f32-argmaxpool-9p8x-rvv-u1v.c
src/f32-avgpool/gen/f32-avgpool-9p-minmax-rvv-u2v.c
src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x2v-rvv-2x2.c
src/f32-dwconv/gen/f32-dwconv-3p8vc-minmax-rvv.c
src/f32-dwconv/gen/f32-dwconv-3p8vc-rvv.c
Expand Down Expand Up @@ -113,12 +114,14 @@ SET(PROD_RVV_MICROKERNEL_SRCS
src/qu8-vlrelu/gen/qu8-vlrelu-rvv-u2v.c
src/qu8-vmul/gen/qu8-vmul-minmax-f32-rvv-u2v.c
src/qu8-vmulc/gen/qu8-vmulc-minmax-f32-rvv-u2v.c
src/s8-maxpool/gen/s8-maxpool-9p-minmax-rvv-u2v.c
src/s8-rdminmax/gen/s8-rdmax-2p2x-rvv-u8v.c
src/s8-rdminmax/gen/s8-rdmin-2p2x-rvv-u8v.c
src/s8-rminmax/gen/s8-rmax-rvv-u8v.c
src/s8-rminmax/gen/s8-rmin-rvv-u8v.c
src/s8-rminmax/gen/s8-rminmax-rvv-u8v.c
src/s8-vclamp/gen/s8-vclamp-rvv-u4v.c
src/u8-maxpool/gen/u8-maxpool-9p-minmax-rvv-u2v.c
src/u8-rdminmax/gen/u8-rdmax-2p2x-rvv-u8v.c
src/u8-rdminmax/gen/u8-rdmin-2p2x-rvv-u8v.c
src/u8-rminmax/gen/u8-rmax-rvv-u8v.c
Expand Down Expand Up @@ -156,7 +159,6 @@ SET(NON_PROD_RVV_MICROKERNEL_SRCS
src/f32-igemm/gen/f32-igemm-1x4v-rvv.c
src/f32-igemm/gen/f32-igemm-7x4v-relu-rvv.c
src/f32-igemm/gen/f32-igemm-7x4v-rvv.c
src/f32-maxpool/gen/f32-maxpool-9p-minmax-rvv-u1v.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-rvv-u1v.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-rvv-u4v.c
src/f32-qs8-vcvt/gen/f32-qs8-vcvt-rvv-u8v.c
Expand Down
2 changes: 2 additions & 0 deletions cmake/gen/rvvfp16arith_microkernels.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@


SET(PROD_RVVFP16ARITH_MICROKERNEL_SRCS
src/f16-avgpool/gen/f16-avgpool-9p-minmax-rvvfp16arith-u2v.c
src/f16-dwconv/gen/f16-dwconv-3p8vc-minmax-rvvfp16arith.c
src/f16-dwconv/gen/f16-dwconv-4p8vc-minmax-rvvfp16arith.c
src/f16-dwconv/gen/f16-dwconv-9p8vc-minmax-rvvfp16arith.c
Expand All @@ -23,6 +24,7 @@ SET(PROD_RVVFP16ARITH_MICROKERNEL_SRCS
src/f16-gemm/gen/f16-gemm-7x4v-minmax-rvvfp16arith.c
src/f16-igemm/gen/f16-igemm-1x4v-minmax-rvvfp16arith.c
src/f16-igemm/gen/f16-igemm-7x4v-minmax-rvvfp16arith.c
src/f16-maxpool/gen/f16-maxpool-9p-minmax-rvvfp16arith-u2v.c
src/f16-rdminmax/gen/f16-rdmax-2p2x-rvvfp16arith-u8v.c
src/f16-rdminmax/gen/f16-rdmin-2p2x-rvvfp16arith-u8v.c
src/f16-rminmax/gen/f16-rmax-rvvfp16arith-u8v.c
Expand Down
4 changes: 3 additions & 1 deletion gen/rvv_microkernels.bzl
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Expand Up @@ -7,6 +7,7 @@

PROD_RVV_MICROKERNEL_SRCS = [
"src/f32-argmaxpool/f32-argmaxpool-9p8x-rvv-u1v.c",
"src/f32-avgpool/gen/f32-avgpool-9p-minmax-rvv-u2v.c",
"src/f32-conv-hwc2chw/f32-conv-hwc2chw-3x3s2p1c3x2v-rvv-2x2.c",
"src/f32-dwconv/gen/f32-dwconv-3p8vc-minmax-rvv.c",
"src/f32-dwconv/gen/f32-dwconv-3p8vc-rvv.c",
Expand Down Expand Up @@ -109,12 +110,14 @@ PROD_RVV_MICROKERNEL_SRCS = [
"src/qu8-vlrelu/gen/qu8-vlrelu-rvv-u2v.c",
"src/qu8-vmul/gen/qu8-vmul-minmax-f32-rvv-u2v.c",
"src/qu8-vmulc/gen/qu8-vmulc-minmax-f32-rvv-u2v.c",
"src/s8-maxpool/gen/s8-maxpool-9p-minmax-rvv-u2v.c",
"src/s8-rdminmax/gen/s8-rdmax-2p2x-rvv-u8v.c",
"src/s8-rdminmax/gen/s8-rdmin-2p2x-rvv-u8v.c",
"src/s8-rminmax/gen/s8-rmax-rvv-u8v.c",
"src/s8-rminmax/gen/s8-rmin-rvv-u8v.c",
"src/s8-rminmax/gen/s8-rminmax-rvv-u8v.c",
"src/s8-vclamp/gen/s8-vclamp-rvv-u4v.c",
"src/u8-maxpool/gen/u8-maxpool-9p-minmax-rvv-u2v.c",
"src/u8-rdminmax/gen/u8-rdmax-2p2x-rvv-u8v.c",
"src/u8-rdminmax/gen/u8-rdmin-2p2x-rvv-u8v.c",
"src/u8-rminmax/gen/u8-rmax-rvv-u8v.c",
Expand Down Expand Up @@ -153,7 +156,6 @@ NON_PROD_RVV_MICROKERNEL_SRCS = [
"src/f32-igemm/gen/f32-igemm-1x4v-rvv.c",
"src/f32-igemm/gen/f32-igemm-7x4v-relu-rvv.c",
"src/f32-igemm/gen/f32-igemm-7x4v-rvv.c",
"src/f32-maxpool/gen/f32-maxpool-9p-minmax-rvv-u1v.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-rvv-u1v.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-rvv-u4v.c",
"src/f32-qs8-vcvt/gen/f32-qs8-vcvt-rvv-u8v.c",
Expand Down
2 changes: 2 additions & 0 deletions gen/rvvfp16arith_microkernels.bzl
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Expand Up @@ -6,6 +6,7 @@
#

PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
"src/f16-avgpool/gen/f16-avgpool-9p-minmax-rvvfp16arith-u2v.c",
"src/f16-dwconv/gen/f16-dwconv-3p8vc-minmax-rvvfp16arith.c",
"src/f16-dwconv/gen/f16-dwconv-4p8vc-minmax-rvvfp16arith.c",
"src/f16-dwconv/gen/f16-dwconv-9p8vc-minmax-rvvfp16arith.c",
Expand All @@ -19,6 +20,7 @@ PROD_RVVFP16ARITH_MICROKERNEL_SRCS = [
"src/f16-gemm/gen/f16-gemm-7x4v-minmax-rvvfp16arith.c",
"src/f16-igemm/gen/f16-igemm-1x4v-minmax-rvvfp16arith.c",
"src/f16-igemm/gen/f16-igemm-7x4v-minmax-rvvfp16arith.c",
"src/f16-maxpool/gen/f16-maxpool-9p-minmax-rvvfp16arith-u2v.c",
"src/f16-rdminmax/gen/f16-rdmax-2p2x-rvvfp16arith-u8v.c",
"src/f16-rdminmax/gen/f16-rdmin-2p2x-rvvfp16arith-u8v.c",
"src/f16-rminmax/gen/f16-rmax-rvvfp16arith-u8v.c",
Expand Down
3 changes: 3 additions & 0 deletions scripts/generate-f16-avgpool.sh
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Expand Up @@ -10,4 +10,7 @@ tools/xngen src/f32-avgpool/avgpool.c.in -D ARCH=neonfp16arith -D DATATYPE=f16 -
##################################### f16c #####################################
tools/xngen src/f16-avgpool/f16c.c.in -D SIMD_SIZE=8 -o src/f16-avgpool/gen/f16-avgpool-9p-minmax-f16c.c &

################################ RISC-V Vector #################################
tools/xngen src/f32-avgpool/rvv.c.in -D DATATYPE=f16 -D LMUL=2 -o src/f16-avgpool/gen/f16-avgpool-9p-minmax-rvvfp16arith-u2v.c &

wait
3 changes: 3 additions & 0 deletions scripts/generate-f16-maxpool.sh
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Expand Up @@ -9,4 +9,7 @@ tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=f16 -D ARCH=neonfp16arith -
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=f16 -D ARCH=avx2 -D SIMD_SIZE=16 -o src/f16-maxpool/gen/f16-maxpool-9p-minmax-avx2-u16.c &
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=f16 -D ARCH=sse41 -D SIMD_SIZE=8 -o src/f16-maxpool/gen/f16-maxpool-9p-minmax-sse41-u8.c &

################################ RISC-V Vector ################################
tools/xngen src/f32-maxpool/rvv.c.in -D DATATYPE=f16 -D LMUL=2 -o src/f16-maxpool/gen/f16-maxpool-9p-minmax-rvvfp16arith-u2v.c &

wait
3 changes: 3 additions & 0 deletions scripts/generate-f32-avgpool.sh
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Expand Up @@ -13,4 +13,7 @@ tools/xngen src/f32-avgpool/avgpool.c.in -D ARCH=avx -D DATATYPE=f32 -D SIM
tools/xngen src/f32-avgpool/avgpool.c.in -D ARCH=avx512f -D DATATYPE=f32 -D SIMD_SIZE=16 -o src/f32-avgpool/gen/f32-avgpool-9p-minmax-avx512f-u16.c &
tools/xngen src/f32-avgpool/avgpool.c.in -D ARCH=hvx -D DATATYPE=f32 -D SIMD_SIZE=32 -o src/f32-avgpool/gen/f32-avgpool-9p-minmax-hvx-u32.c &

################################ RISC-V Vector ################################
tools/xngen src/f32-avgpool/rvv.c.in -D DATATYPE=f32 -D LMUL=2 -o src/f32-avgpool/gen/f32-avgpool-9p-minmax-rvv-u2v.c &

wait
3 changes: 1 addition & 2 deletions scripts/generate-f32-maxpool.sh
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Expand Up @@ -12,7 +12,6 @@ tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=f32 -D ARCH=neon -D SIM
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=f32 -D ARCH=hvx -D SIMD_SIZE=32 -o src/f32-maxpool/gen/f32-maxpool-9p-minmax-hvx-u32.c &

################################ RISC-V Vector ################################
tools/xngen src/f32-maxpool/rvv.c.in -D LMUL=1 -o src/f32-maxpool/gen/f32-maxpool-9p-minmax-rvv-u1v.c &
tools/xngen src/f32-maxpool/rvv.c.in -D LMUL=2 -o src/f32-maxpool/gen/f32-maxpool-9p-minmax-rvv-u2v.c &
tools/xngen src/f32-maxpool/rvv.c.in -D DATATYPE=f32 -D LMUL=2 -o src/f32-maxpool/gen/f32-maxpool-9p-minmax-rvv-u2v.c &

wait
3 changes: 3 additions & 0 deletions scripts/generate-s8-maxpool.sh
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Expand Up @@ -10,4 +10,7 @@ tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=s8 -D ARCH=sse41 -D SIMD_SI
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=s8 -D ARCH=wasmsimd -D SIMD_SIZE=16 -o src/s8-maxpool/gen/s8-maxpool-9p-minmax-wasmsimd-u16.c &
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=s8 -D ARCH=neon -D SIMD_SIZE=16 -o src/s8-maxpool/gen/s8-maxpool-9p-minmax-neon-u16.c &

################################ RISC-V Vector #################################
tools/xngen src/f32-maxpool/rvv.c.in -D DATATYPE=s8 -D LMUL=2 -o src/s8-maxpool/gen/s8-maxpool-9p-minmax-rvv-u2v.c &

wait
3 changes: 3 additions & 0 deletions scripts/generate-u8-maxpool.sh
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Expand Up @@ -10,4 +10,7 @@ tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=u8 -D KERNEL_TILE=9 -D ARCH
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=u8 -D KERNEL_TILE=9 -D ARCH=wasmsimd -D SIMD_SIZE=16 -o src/u8-maxpool/gen/u8-maxpool-9p-minmax-wasmsimd-u16.c &
tools/xngen src/f32-maxpool/maxpool.c.in -D DATATYPE=u8 -D KERNEL_TILE=9 -D ARCH=neon -D SIMD_SIZE=16 -o src/u8-maxpool/gen/u8-maxpool-9p-minmax-neon-u16.c &

################################ RISC-V Vector #################################
tools/xngen src/f32-maxpool/rvv.c.in -D DATATYPE=u8 -D LMUL=2 -o src/u8-maxpool/gen/u8-maxpool-9p-minmax-rvv-u2v.c &

wait
17 changes: 17 additions & 0 deletions src/configs/avgpool-config.c
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Expand Up @@ -51,6 +51,16 @@ static void init_f16_avgpool_config(void) {
} else
#endif
; // no f16 support
#elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config();
assert(hardware_config != NULL);
(void) hardware_config; // May be unused.
if (hardware_config->arch_flags & xnn_arch_riscv_vector_fp16_arith) {
f16_avgpool_config.ukernel = XNN_INIT_AVGPOOL_UKERNEL(xnn_f16_avgpool_minmax_ukernel_9p__rvvfp16arith_u2v);
f16_avgpool_config.init.f16 = xnn_init_f16_scaleminmax_scalar_params;
f16_avgpool_config.primary_tile = 9;
f16_avgpool_config.channel_tile = 2 * hardware_config->vlenb / sizeof(xnn_float16);
}
#endif
}

Expand Down Expand Up @@ -123,6 +133,13 @@ static void init_f32_avgpool_config(void) {
f32_avgpool_config.primary_tile = 9;
f32_avgpool_config.channel_tile = 32;
}
#elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR
const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config();
assert(hardware_config != NULL);
f32_avgpool_config.ukernel = XNN_INIT_AVGPOOL_UKERNEL(xnn_f32_avgpool_minmax_ukernel_9p__rvv_u2v);
f32_avgpool_config.init.f32 = xnn_init_f32_scaleminmax_scalar_params;
f32_avgpool_config.primary_tile = 9;
f32_avgpool_config.channel_tile = 2 * hardware_config->vlenb / sizeof(float);
#else
f32_avgpool_config.ukernel = XNN_INIT_AVGPOOL_UKERNEL(xnn_f32_avgpool_minmax_ukernel_9p__scalar_u1);
f32_avgpool_config.init.f32 = xnn_init_f32_scaleminmax_scalar_params;
Expand Down
14 changes: 14 additions & 0 deletions src/configs/maxpool-config.c
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Expand Up @@ -65,6 +65,14 @@ static void init_f16_maxpool_config(void) {
} else
#endif
; // no f16 support
#elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
const struct xnn_hardware_config* hardware_config = xnn_init_hardware_config();
assert(hardware_config != NULL);
(void) hardware_config; // May be unused.
if (hardware_config->arch_flags & xnn_arch_riscv_vector_fp16_arith) {
f16_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_f16_maxpool_minmax_ukernel_9p__rvvfp16arith_u2v);
f16_maxpool_config.init.f16 = xnn_init_f16_minmax_scalar_params;
}
#endif
}

Expand Down Expand Up @@ -144,6 +152,9 @@ static void init_s8_maxpool_config(void) {
#elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
s8_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_s8_maxpool_minmax_ukernel_9p__wasmsimd_u16);
s8_maxpool_config.init.s8 = xnn_init_s8_minmax_scalar_params;
#elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR
s8_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_s8_maxpool_minmax_ukernel_9p__rvv_u2v);
s8_maxpool_config.init.s8 = xnn_init_s8_minmax_scalar_params;
#else
s8_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_s8_maxpool_minmax_ukernel_9p__scalar_u1);
s8_maxpool_config.init.s8 = xnn_init_s8_minmax_scalar_params;
Expand Down Expand Up @@ -178,6 +189,9 @@ static void init_u8_maxpool_config(void) {
#elif XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD
u8_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_u8_maxpool_minmax_ukernel_9p__wasmsimd_u16);
u8_maxpool_config.init.u8 = xnn_init_u8_minmax_scalar_params;
#elif XNN_ARCH_RISCV && XNN_ENABLE_RISCV_VECTOR
u8_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_u8_maxpool_minmax_ukernel_9p__rvv_u2v);
u8_maxpool_config.init.u8 = xnn_init_u8_minmax_scalar_params;
#else
u8_maxpool_config.ukernel = XNN_INIT_MAXPOOL_UKERNEL(xnn_u8_maxpool_minmax_ukernel_9p__scalar_u1);
u8_maxpool_config.init.u8 = xnn_init_u8_minmax_scalar_params;
Expand Down
4 changes: 4 additions & 0 deletions src/f16-avgpool/f16-avgpool-minmax.inc
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Expand Up @@ -14,3 +14,7 @@ XNN_UKERNEL(xnn_arch_arm_neon_fp16_arith, xnn_f16_avgpool_minmax_ukernel_9p__neo
#if XNN_ENABLE_F16C && (XNN_ARCH_X86 || XNN_ARCH_X86_64)
XNN_UKERNEL(xnn_arch_x86_f16c, xnn_f16_avgpool_minmax_ukernel_9p__f16c_u8, 8, 9, xnn_float16, struct xnn_f16_scaleminmax_params, xnn_init_f16_scaleminmax_scalar_params)
#endif // XNN_ENABLE_F16C && (XNN_ARCH_X86 || XNN_ARCH_X86_64)

#if XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
XNN_UKERNEL(xnn_arch_riscv_vector_fp16_arith, xnn_f16_avgpool_minmax_ukernel_9p__rvvfp16arith_u2v, (2*xnn_init_hardware_config()->vlenb/sizeof(xnn_float16)), 9, xnn_float16, struct xnn_f16_scaleminmax_params, xnn_init_f16_scaleminmax_scalar_params)
#endif // XNN_ARCH_RISCV && XNN_ENABLE_RISCV_FP16_VECTOR
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