fix(shader): correct pI1→pI2 variable in dual-issue decode stats

[eunseo9311]

Summary

Fix an incorrect variable reference in shader_core_ctx::decode() that causes wrong instruction type statistics to be recorded for the second instruction in dual-issue scenarios.

Problem

In shader.cc lines 911–912, the operand type check for the second decoded instruction (pI2) incorrectly references pI1:

// Before (buggy)
if ((pI1->oprnd_type == INT_OP) ||
    (pI1->oprnd_type == UN_OP)) {   // ← should be pI2
    m_stats->m_num_INTdecoded_insn[m_sid]++;
} else if (pI2->oprnd_type == FP_OP) {
    m_stats->m_num_FPdecoded_insn[m_sid]++;
}

This causes m_num_INTdecoded_insn to be incremented based on pI1's operand type when classifying pI2, silently producing incorrect decode statistics for dual-issued instructions. The bug is latent — it only manifests when both instructions are decoded in the same cycle and their operand types differ.

Fix

// After
if ((pI2->oprnd_type == INT_OP) ||
    (pI2->oprnd_type == UN_OP)) {
    m_stats->m_num_INTdecoded_insn[m_sid]++;
} else if (pI2->oprnd_type == FP_OP) {
    m_stats->m_num_FPdecoded_insn[m_sid]++;
}

Impact

• No behavioral change to simulation execution — only statistics counters are affected
• Simulation output (IPC, memory access patterns, functional correctness) is unchanged
• Decode statistics (m_num_INTdecoded_insn, m_num_FPdecoded_insn) will now correctly reflect the second instruction's operand type in dual-issue scenarios
• These counters feed into McPAT/AccelWattch for scheduler power estimation

Testing

Verified with Rodinia 2.0 hotspot benchmark on GTX1080Ti config. Simulation output log is identical; only per-SM decode stat counters change for workloads with dual-issued mixed INT/FP instruction pairs.

source setup_environment release
make -j
# Run any CUDA workload with dual-issue enabled and inspect
# gpgpu_stats output for m_num_INTdecoded_insn / m_num_FPdecoded_insn