siracusa: integrate Light_RedMulE accelerator

[runwangdl]

Summary

Integrates the existing Light_RedMulE model (pulp/light_redmule/) into the Siracusa cluster as a memory-mapped accelerator, mutually exclusive with Neureka (they share the L1 neureka_in TCDM ingress port). Selection is controlled from Python via an accelerator kwarg, defaulting to neureka so current behaviour is unchanged.

Changes

• pulp/chips/siracusa/cluster.py:
  • New accelerator kwarg on Cluster.__init__ (values: 'neureka' | 'redmule'). Falls back to the accelerator key in cluster.json, then to 'neureka'.
  • Exactly one of Neureka / Light_RedMulE is instantiated; all its bindings (wmem out, periph_ico mapping, IRQ, TCDM neureka_in) are gated behind the selection.
• pulp/chips/siracusa/pulp_open.py: propagate the same accelerator kwarg to the Cluster call, so callers (e.g. Pulp_open_board) can select via Python without editing cluster.json.
• pulp/chips/siracusa/cluster.json:
  • Default "accelerator": "neureka" to preserve existing behaviour.
  • New redmule peripheral entry at 0x10201C00 (size 0x200) with a Light_RedMulE configuration (elem_size=4, ce_height=12, ce_width=4, queue depth 8), used only when the accelerator is switched to redmule.

Usage

# Default (unchanged): Neureka
Pulp_open(parent, 'chip', parser)
# Opt-in Light_RedMulE variant
Pulp_open(parent, 'chip', parser, accelerator='redmule')

Why

Unblocks Deeploy support for a new Siracusa_w_redmule target: the compiler needs the accelerator visible in the Siracusa chip model so generated C code can issue the Light_RedMulE register sequence. The Deeploy side of the integration (MAGIA-style register protocol matching PR #70's I_INPUT_V2) is a separate downstream change.

Scope & compatibility

• Non-invasive: no changes to pulp/light_redmule/, Neureka, or cluster infrastructure.
• Default accelerator='neureka' keeps every existing siracusa consumer bit-identical.
• Switching to redmule disables Neureka (including its wmem_out, IRQ and neureka_in bindings) in the same cluster.

Testing

Builds cleanly under make TARGETS="siracusa" on current master in both modes. End-to-end validation (Deeploy testFloatMatmul through GVSoC on the redmule variant) is pending the companion Deeploy-side PR; this change stands alone as a Siracusa configuration update.