UCIe Reliability Lab

A reliability laboratory for Universal Chiplet Interconnect Express (UCIe) die-to-die links, with thirteen analytical & Monte-Carlo modules and an interactive Streamlit dashboard.

This is the open-source companion artefact for the IEEE Access survey "Error Detection and Correction in UCIe Chiplet Interconnects: A Comprehensive Survey" (Iyar, Nayak, Jatti, 2026). The code reproduces every figure in the paper, validates every analytical bound against Monte Carlo, and exposes the entire reliability budget through a slider-driven web dashboard so non-specialists can explore the design space.

What's inside

Five new analytical/simulation modules added in this revision:

Module	What it answers	Reviewer point addressed
src/multi_hop.py	How does residual error grow across a 2-, 3-, or N-hop CXL.mem path, and how much does an end-to-end CRC layer help?	Multi-hop SDC, previously listed as "open problem"
src/replay_buffer.py	What does the replay-buffer occupancy actually look like under bursty channels — Markov chain dynamics, not just the worst-case-product bound?	Replay-buffer hand-wave deepened to a real analysis
src/correlated_defects.py	When defects cluster spatially (substrate warpage) and spare assignment is adjacency-constrained, how badly does the binomial Eq.(5) bound break?	M9 — independence assumption is wrong
src/fec_pipeline.py	Decomposes the PCIe-6.0 FEC-then-CRC pipeline layer by layer, including FEC miscorrection bounds (Wicker 1995)	Deepen the simulator beyond textbook math
src/ber_to_compliance.py	Maps VTF compliance margin (dB) to BER via Q-function so thermal-drift figures derive from the quantity the spec measures	M10 — calibrate the thermal model

Plus the eight original modules (flit, channel, analytical, lane_repair, fec, retry, aggregator, plotting) that produced the paper's Figures 3–7 and Table 2.

Run the interactive demo

streamlit run app.py

Opens a browser dashboard at http://localhost:8501 with six labs, each tied to a slider-driven reproduction of one part of the paper:

1. Single-link CRC sizing — pick a flit format & BER, see the residual undetected-error rate live-update.
2. Multi-hop residual (CXL.mem) — chain 2–6 UCIe hops, toggle end-to-end CRC width, watch the silent-data-corruption probability collapse by 10⁹×.
3. Replay-buffer dynamics — Monte Carlo of buffer occupancy under three channel models (uniform, Gilbert–Elliott, deterministic burst).
4. Lane repair under defects — compare the binomial-CDF baseline with cluster + adjacency-constrained repair on a 2D lane grid.
5. FEC-vs-CRC trade — see PCIe 6.0's FEC-then-CRC pipeline decomposed layer by layer; identify the BER crossover.
6. Thermal drift — drive the link with a margin-domain thermal trace; tune the recalibration interval.

Every lab has a plain-English "Takeaway" box that translates the plot into a one-sentence engineering interpretation.

Folder layout

ucie_reliability_sim/
├── app.py                           Streamlit dashboard (six labs)
├── run_all.py                       CLI: tests + all 10 figures + Table 2
├── requirements.txt                 numpy, matplotlib, scipy, streamlit, plotly
├── README.md                        this file
├── LICENSE                          MIT
├── CITATION.cff                     GitHub citation metadata
│
├── src/                             13 modules (8 original + 5 new)
│   ├── flit.py                      UCIE_FLIT_FORMATS: Fmt1..Fmt6
│   ├── channel.py                   Uniform, Gilbert-Elliott, ThermalDrift
│   ├── analytical.py                Eqs. (3), (4); burst-detection bounds
│   ├── lane_repair.py               Binomial link-survival + MC trials
│   ├── fec.py                       RS GF(2^8) interleaved residual
│   ├── retry.py                     SimConfig / simulate(): event-level core
│   ├── aggregator.py                Sweep helpers
│   ├── plotting.py                  IEEE single-column style
│   ├── multi_hop.py                 [NEW] end-to-end CRC composition
│   ├── replay_buffer.py             [NEW] Markov replay-buffer dynamics
│   ├── correlated_defects.py        [NEW] 2D lane grid + spatial models
│   ├── fec_pipeline.py              [NEW] FEC-then-CRC + miscorrection bound
│   └── ber_to_compliance.py         [NEW] VTF margin <-> BER via Q-function
│
├── experiments/                     One script per paper figure
│   ├── fig_a_retry_vs_ber.py        Figure 3
│   ├── fig_b_latency_vs_ber.py      Figure 5
│   ├── fig_c_lane_repair.py         Figure 6
│   ├── fig_d_undetected_error_bound.py  Figure 4
│   ├── fig_e_thermal_drift.py       Figure 7 (legacy)
│   ├── fig_f_multi_hop_residual.py  [NEW] multi-hop residual
│   ├── fig_g_replay_buffer_occupancy.py  [NEW] buffer dynamics
│   ├── fig_h_correlated_defects.py  [NEW] cluster vs binomial
│   ├── fig_i_fec_pipeline.py        [NEW] PCIe FEC pipeline
│   ├── fig_j_compliance_ber.py      [NEW] margin -> BER + thermal drift
│   └── table_ii_residual_error.py   Table 2 (CSV + LaTeX)
│
├── tests/                           54 unit tests across 8 test files
│   ├── test_channel.py              channel statistics
│   ├── test_analytical.py           closed-form bounds
│   ├── test_lane_repair.py          binomial CDF
│   ├── test_fec.py                  RS residual monotonicity
│   ├── test_multi_hop.py            [NEW] hop composition + sweeps
│   ├── test_replay_buffer.py        [NEW] buffer Markov chain
│   ├── test_correlated_defects.py   [NEW] defect models + repair
│   └── test_fec_and_compliance.py   [NEW] FEC pipeline + Q-function
│
├── configs/
│   └── default.yaml                 Default link parameters
├── docs/
│   └── METHODOLOGY.md               Methodology, scope, limitations
└── results/
    ├── figures/                     10 figures (PNG + vector PDF)
    └── tables/                      CSV + LaTeX booktabs outputs

Installation

Tested with Python 3.10+ on Linux/macOS.

git clone https://github.com/harineee/ucie_reliability_sim.git
cd ucie_reliability_sim
python -m venv .venv && source .venv/bin/activate
pip install -r requirements.txt

For headless reproduction (no dashboard), only numpy, matplotlib, and scipy are required.

Reproduce every paper figure (CLI)

python run_all.py                  # tests + all 10 figures + Table 2
python run_all.py --tests-only     # 54 unit tests, ~1 s
python run_all.py --figs-only      # skip tests, regenerate figures
python run_all.py --figure F       # just the multi-hop residual figure

End-to-end runtime is roughly 45 seconds on a commodity laptop.

What each figure shows

Paper Fig	Script	Headline argument
Fig 3	fig_a_retry_vs_ber	Retry rate matches L·BER across uniform + bursty channels
Fig 4	fig_d_undetected_error_bound	A 16-bit CRC is the only realistic UCIe residual exposure
Fig 5	fig_b_latency_vs_ber	FEC pays fixed latency; retry pays only on errors → crossover ~10⁻⁴
Fig 6	fig_c_lane_repair	Two spare lanes carry a 64-lane module to 6-nines link yield
Fig 7	fig_e_thermal_drift	1-s recal interval keeps mean BER within 2× of cold-start
Fig F (new)	fig_f_multi_hop_residual	32-bit E2E CRC stitching gives 4.3×10⁹-fold residual attenuation across a 2-hop CXL.mem path
Fig G (new)	fig_g_replay_buffer_occupancy	Buffer depth ≥ t_rt is sufficient; head-of-line blocking dominates over channel stats
Fig H (new)	fig_h_correlated_defects	Cluster + adjacent-only repair fails 80× more often than the binomial baseline at 1% defect rate
Fig I (new)	fig_i_fec_pipeline	PCIe 6.0's CRC backstop turns a 10⁻²⁵ FEC-miscorrection rate into a 10⁻²⁸ silent-corruption rate
Fig J (new)	fig_j_compliance_ber	1 dB of compliance margin buys ~3 orders of BER headroom through the Q-function

Headline numerical results

These are the quantitative claims the revised paper cites, all reproducible by running the corresponding script:

• Two-hop CXL.mem residual (compute → retimer → memory expander), BER = 10⁻¹², 32-bit per-hop CRC:

  • Without end-to-end CRC: 9.5 × 10⁻¹⁹
  • With 32-bit E2E CRC: 2.2 × 10⁻²⁸
  • Improvement factor: 4.3 × 10⁹ ×

• PCIe 6.0 at BER = 10⁻⁶, RS(255,252) over GF(2⁸) with 3× interleave + 64-bit CRC: P(silent corruption) = 3.4 × 10⁻²⁵.

• UCIe 3.0 at BER = 10⁻¹², CRC only (no FEC), 64-bit Fmt-5 CRC: P(silent corruption) = 1.1 × 10⁻²⁸.

• Cluster + adjacent-only repair at p_def = 1%: ~14% survival vs >99.99% for independent + global-pool — the binomial baseline is ~85 percentage points optimistic in this regime.

Scope and limitations

This is a collection of analytical and Monte Carlo Python scripts. It is not an RTL implementation of a UCIe CRC engine, not a cycle-accurate D2D adapter model, and not a calibrated channel simulator at the SerDes level. The Gilbert–Elliott channel is a two-state Markov toy; the thermal-drift channel is a sensitivity tool, not an empirically calibrated model.

What the artefact does provide:

• A reproducible, parameter-sweep-friendly implementation of the paper's analytical bounds.
• Monte Carlo cross-checks at the flit granularity wherever closed-form bounds exist.
• Five novel analyses — multi-hop CRC composition, Markov replay buffer, correlated-defect lane repair, FEC-then-CRC pipeline, margin-to-BER mapping — that quantify what the paper's prior revisions hand-waved.

Validation

python -m pytest tests/ -q          # 54 tests, ~1 s

The most important test is test_analytical.py::test_mc_matches_analytical_uniform, which sweeps BER ∈ {10⁻⁷, 10⁻⁶, 10⁻⁵} and confirms that Monte Carlo retry counts agree with the closed-form 1 − (1 − BER)^L within MC noise. The new modules add 28 further tests across multi-hop composition, buffer dynamics, defect models, FEC pipeline arithmetic, and Q-function round-trips.

Reproducibility

Every script uses a fixed numpy.random.SeedSequence. Re-running python run_all.py on the same machine reproduces every CSV and figure byte-for-byte.

Citing

@article{iyar2026ucie,
  author  = {Iyar, Harini G. and Nayak, Sagar and Jatti, Anand},
  title   = {Error Detection and Correction in UCIe Chiplet Interconnects:
             A Comprehensive Survey},
  journal = {IEEE Access},
  year    = {2026},
}

A CITATION.cff is included for GitHub's "Cite this repository" sidebar.

License

MIT — see LICENSE.