Out-of-Order support

pasim

@@ -16,6 +16,8 @@ import argparse
 import os
 import sys
 
+from pyArchSimLib.proc import FiveStageInorderProcessor, OutOfOrderProcessor
+
 # Constants
 ROOT_INDICATOR = '.__PYTHON_ROOT__'
 
@@ -51,6 +53,7 @@ parser.add_argument('asm_file')
 parser.add_argument('-m', '--max-num-cycles', type=int, default=1000000)
 parser.add_argument('-l', '--linetrace', action='store_true')
 parser.add_argument('-f', '--linetrace-file', type=str)
+parser.add_argument('--ooo', action='store_true', help='Use the Out-of-Order core')
 
 # Parse the arguments
 args = parser.parse_args()
@@ -64,7 +67,24 @@ if ltFilename: ltFile = open(ltFilename, 'w')
 
 # System and assembler
 assemblerObj = assembler(mips32)
-system       = BasicSystem(ltEnable)
+# system       = BasicSystem(ltEnable)
+
+# Pick in-order vs. OoO core
+if args.ooo:
+  proc = OutOfOrderProcessor()
+else:
+  proc = FiveStageInorderProcessor()
+
+# Build the system around that proc
+system = BasicSystem(ltEnable)
+system.proc = proc
+# Re-wire the memory interfaces
+system.proc.setMemCanReq   (system.mem.canReq)
+system.proc.setMemSendReq  (system.mem.sendReq)
+system.proc.setMemHasResp  (system.mem.hasResp)
+system.proc.setMemRecvResp (system.mem.recvResp)
+system.proc.setMemReadFunct (system.mem.read)
+system.proc.setMemWriteFunct(system.mem.write)
 
 # Open the assembly file
 asmFilename = args.asm_file

pyArchSimLib/proc/OoO_proc.py

@@ -0,0 +1,42 @@
+# pyArchSimLib/proc/oOo_processor.py
+
+from pyArchSimLib.proc.core import OoOCore
+from pyArchSimLib.mem.cache   import NoCache
+
+class OutOfOrderProcessor:
+    def __init__(self):
+        self.core   = OoOCore()
+        self.icache = NoCache(0)
+        self.dcache = NoCache(1)
+
+        # hook up instruction port
+        self.core.setIMemCanReq   (self.icache.canReq)
+        self.core.setIMemSendReq  (self.icache.sendReq)
+        self.core.setIMemHasResp  (self.icache.hasResp)
+        self.core.setIMemRecvResp (self.icache.recvResp)
+        # hook up data port
+        self.core.setDMemCanReq   (self.dcache.canReq)
+        self.core.setDMemSendReq  (self.dcache.sendReq)
+        self.core.setDMemHasResp  (self.dcache.hasResp)
+        self.core.setDMemRecvResp (self.dcache.recvResp)
+
+    def setMemReadFunct(self, f):   self.core.setMemReadFunct(f)
+    def setMemWriteFunct(self, f):  self.core.setMemWriteFunct(f)
+    def setMemCanReq(self,  f):     self.icache.setMemCanReq(f); self.dcache.setMemCanReq(f)
+    def setMemSendReq(self, f):     self.icache.setMemSendReq(f); self.dcache.setMemSendReq(f)
+    def setMemHasResp(self, f):     self.icache.setMemHasResp(f); self.dcache.setMemHasResp(f)
+    def setMemRecvResp(self,f):     self.icache.setMemRecvResp(f);self.dcache.setMemRecvResp(f)
+
+    def roiFlag(self):           return self.core.roiFlag()
+    def instCompletionFlag(self): return self.core.instCompletionFlag()
+    def getExitStatus(self):    return self.core.getExitStatus()
+
+    def tick(self):
+        # advance OoO pipeline
+        self.core.tick()
+        self.icache.tick()
+        self.dcache.tick()
+
+    def linetrace(self):
+        # combine core + caches if you like
+        return self.core.linetrace()

pyArchSimLib/proc/__init__.py

@@ -1 +1,2 @@
 from .five_stage_proc import FiveStageInorderProcessor
+from .OoO_proc        import OutOfOrderProcessor