Chipathon2024 Mahowald-ers Cascode Common Source Block by Sud-ana · Pull Request #339 · idea-fasoc/OpenFASOC

Sud-ana · 2024-09-23T23:15:00Z

PR for a cascode common source . LVS is failing with Final result: Top level cell failed pin matching. Please review and let us know the function parameters for LVS.

…ove the M2 north of M1.

…horizontal or vertical placement.

Sud-ana · 2024-09-23T23:28:25Z

@chetanyagoyal / @srpathen ,
LVS check is failing for this cell with error as Top level cell failed pin matching. Could you kindly help review the pin assignment function so that LVS succeeds ?

`Circuit 1 contains 6 devices, Circuit 2 contains 2 devices. *** MISMATCH ***
Circuit 1 contains 10 nets, Circuit 2 contains 5 nets. *** MISMATCH ***

Final result:
Top level cell failed pin matching.

Logging to file "/tmp/tmp4n_a1thr/cascode_common_source_lvs_lvs.rpt" disabled
LVS Done.

Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.
Flattening unmatched subcell Unnamed_c9b8b1be in circuit cascode_common_source_lvs (0)(1 instance)
Flattening unmatched subcell Unnamed_a576aef1 in circuit cascode_common_source_lvs (0)(1 instance)

Class cascode_common_source_lvs (0): Merged 8 parallel devices.
Subcircuit summary:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
sky130_fd_pr__nfet_01v8 (14->6)	sky130_fd_pr__nfet_01v8 (20->2) **Mismatch
Number of devices: 6 Mismatch	Number of devices: 2 Mismatch
Number of nets: 10 Mismatch	Number of nets: 5 Mismatch

NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: cascode_common_source_lvs |Circuit 2: cascode_common_source_lvs

Net: w_n780_n522# |Net: IOUT
sky130_fd_pr__nfet_01v8/4 = 6 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
Net: /Unnamed_c9b8b1be_0/a_n370_n286# |Net: VSS
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
| sky130_fd_pr__nfet_01v8/4 = 2
|
Net: /Unnamed_a576aef1_0/a_n245_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 1 |
|
Net: /Unnamed_c9b8b1be_0/a_498_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |
|
Net: /Unnamed_c9b8b1be_0/a_n718_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |
|
Net: /Unnamed_a576aef1_0/a_498_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |
|
Net: /Unnamed_a576aef1_0/a_n718_n286# |(no matching net)
sky130_fd_pr__nfet_01v8/(1|3) = 2 |
sky130_fd_pr__nfet_01v8/2 = 1 |

DEVICE mismatches: Class fragments follow (with node fanout counts):
Circuit 1: cascode_common_source_lvs |Circuit 2: cascode_common_source_lvs

Instance: Unnamed_c9b8b1be_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|
|
Instance: Unnamed_c9b8b1be_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|
|
Instance: Unnamed_a576aef1_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|
|
Instance: Unnamed_a576aef1_0/sky130_fd_pr_ |(no matching instance)
(1,3) = (3,3) |
2 = 3 |
4 = 6 |
|

Netlists do not match.

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
(no matching pin)	VIN
(no matching pin)	VBIAS
(no matching pin)	VSS
(no matching pin)	IOUT
proxyIOUT	(no matching pin)

Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Top level cell failed pin matching.
`

Sud-ana · 2024-10-09T23:05:49Z

I've added the rectangular Pins and labels using add_label() and align_comp_to_port(). As a result the label and rectangular ports are visible on metal 1 as shown below. However, LVS is still failing as the export component doesn't recognize the ports as components.

`
Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
(no matching pin)	VIN
(no matching pin)	VBIAS
(no matching pin)	VSS
(no matching pin)	IOUT
proxyIOUT	(no matching pin)

Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Top level cell failed pin matching.

`

chetanyagoyal · 2024-10-17T15:17:06Z

use this extraction script

Sud-ana · 2024-10-17T15:26:12Z

@chetanyagoyal could you kindly clarify the netlist function used for the LVS check as the lvs fail implies that the Netlist is not getting extracted with the correct pins.

` return Netlist(
circuit_name='',
nodes=['VIN', 'VBIAS', 'VSS', 'IOUT'],
source_netlist=source_netlist,
instance_format=instance_format,
parameters={
'model': model,
'width': width,
'length': length,
'mult': multipliers
}
)

`

Also the extract scipt gave the following error whenused with the gds

`
./extract.bash.tempate.sh: line 13: paropt: command not found

Magic 8.3 revision 464 - Compiled on Sat Mar 9 23:18:29 UTC 2024.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Using technology "minimum", version 0.0
Don't know how to read GDS-II:
Nothing in "cifinput" section of tech file.
Warning: There is nothing here to extract.
Total Nodes: 0
`

chetanyagoyal · 2024-11-01T12:29:29Z

@chetanyagoyal could you kindly clarify the netlist function used for the LVS check as the lvs fail implies that the Netlist is not getting extracted with the correct pins.

` return Netlist( circuit_name='', nodes=['VIN', 'VBIAS', 'VSS', 'IOUT'], source_netlist=source_netlist, instance_format=instance_format, parameters={ 'model': model, 'width': width, 'length': length, 'mult': multipliers } )

`

Also the extract scipt gave the following error whenused with the gds

` ./extract.bash.tempate.sh: line 13: paropt: command not found

Magic 8.3 revision 464 - Compiled on Sat Mar 9 23:18:29 UTC 2024. Starting magic under Tcl interpreter Using the terminal as the console. Using NULL graphics device. Processing system .magicrc file Using technology "minimum", version 0.0 Don't know how to read GDS-II: Nothing in "cifinput" section of tech file. Warning: There is nothing here to extract. Total Nodes: 0 `

Apologies for the late replies, you can just dump the netlist from the python function to a file (top_level.info['netlist'].generate_netlist() should return a string).

Try modifying the function until the dumped netlist matches your expectations

chetanyagoyal

Please address the comments and look through the code in the repo to debug, let us know if youre stuck after this

Sud-ana · 2024-11-28T01:46:47Z

LVS checks are in progress. Have added the ports to the layout .

LVS checks are still failing.
`Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.

Subcircuit summary:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
sky130_fd_pr__nfet_01v8 (2)	sky130_fd_pr__nfet_01v8 (2)
Number of devices: 2	Number of devices: 2
Number of nets: 6 Mismatch	Number of nets: 5 Mismatch

NET mismatches: Class fragments follow (with fanout counts):
Circuit 1: cascode_common_source_lvs |Circuit 2: cascode_common_source_lvs

Net: IOUT |Net: IOUT
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
Net: VSS |Net: VSS
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
| sky130_fd_pr__nfet_01v8/4 = 2
|
Net: w_n386_n737# |(no matching net)
sky130_fd_pr__nfet_01v8/4 = 2 |

Netlists do not match.

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
(no pins)	VBIAS Mismatch
(no matching pin)	VIN
(no matching pin)	VSS
(no matching pin)	IOUT
(no matching pin)	INT

Cell pin lists for cascode_common_source_lvs and cascode_common_source_lvs altered to match.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Top level cell failed pin matching.`

Unable to store the LVS, DRC results in DRC, LVS directory as I see error below
magic_drc_result = sky130.drc_magic(Cascode_cs_component, Cascode_cs_component.name, output_file_path="DRC/") File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 55, in wrapper_function return vd.call(*args, **kwargs) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 149, in call m = self.init_model_instance(*args, **kwargs) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 146, in init_model_instance return self.model(**values) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/main.py", line 209, in __init__ validated_self = self.__pydantic_validator__.validate_python(data, self_instance=self) File "/usr/bin/miniconda3/lib/python3.10/site-packages/pydantic/deprecated/decorator.py", line 255, in check_kwargs raise TypeError(f'unexpected keyword argument{plural}: {keys}') TypeError: unexpected keyword argument: 'output_file_path'

…LVS but netlist fails to match. Debug required.

Sud-ana · 2024-12-08T06:56:08Z

The LVS passes when all the bulks are tied to VSS for NMOS, but I cannot short the M2 bulk to M2 source. The LVS fails when each bulk is connected to it's source ports. Please feedback on how to short the bulk to the source.

`Logging to file "/tmp/tmp79w4dkic/cascode_common_source_lvs_lvs.rpt" disabled
LVS Done.

Circuit 1 cell sky130_fd_pr__nfet_01v8 and Circuit 2 cell sky130_fd_pr__nfet_01v8 are black boxes.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.
Warning: Equate pins: cell sky130_fd_pr__nfet_01v8 is a placeholder, treated as a black box.

Subcircuit pins:

Circuit 1: sky130_fd_pr__nfet_01v8	Circuit 2: sky130_fd_pr__nfet_01v8
1	1
2	2
3	3
4	4

Cell pin lists are equivalent.
Device classes sky130_fd_pr__nfet_01v8 and sky130_fd_pr__nfet_01v8 are equivalent.

Subcircuit summary:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
sky130_fd_pr__nfet_01v8 (2)	sky130_fd_pr__nfet_01v8 (2)
Number of devices: 2	Number of devices: 2
Number of nets: 5	Number of nets: 5

Netlists match uniquely.

Subcircuit pins:

Circuit 1: cascode_common_source_lvs	Circuit 2: cascode_common_source_lvs
VSS	VSS
VIN	VIN
IOUT	IOUT
VBIAS	VBIAS
INT	INT

Cell pin lists are equivalent.
Device classes cascode_common_source_lvs and cascode_common_source_lvs are equivalent.

Final result: Circuits match uniquely.
.
`

harshkhandeparkar · 2024-12-12T09:22:56Z

+
+	instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}"
+
+	return Netlist(


You do not need to construct the whole netlist. You can use the sub-devices (the NMOS) and use python to construct the netlist.

OpenFASOC/openfasoc/generators/glayout/glayout/flow/spice/netlist.py

Line 142 in e7f4611

def connect_node(

Thanks, sure have tried to use this.

def cascode_common_source_netlist( ) -> Netlist: fet_type = 'nfet' if 'n' in n_or_p_fet else 'pfet' csrc_netlist=Netlist(circuit_name='CASCODECOMMONSRC', nodes=['VIN', 'VBIAS', 'VSS', 'IOUT', "INT"]) csrc_netlist.connect_node(fet_netlist(pdk=pdk, circuit_name= "M1", model= pdk.models[fet_type], width= 3, length= None, fingers= 1, multipliers= m1_fingers, with_dummy= False), node_mapping= [("D","INT"), ("G","VIN"), ("S", "VSS"), ("B","VSS")] ) csrc_netlist.connect_node(fet_netlist(pdk=pdk, circuit_name= "M2", model= pdk.models[fet_type], width= 3, length= None, fingers= 1, multipliers= m2_fingers, with_dummy= False), node_mapping= [("D","IOUT"), ("G","VBIAS"), ("S", "INT"), ("B","INT")] ) return csrc_netlist

I see an error as below:
File "/usr/bin/miniconda3/lib/python3.10/site-packages/glayout/flow/spice/netlist.py", line 153, in connect_node net_index = net if type(net) == int else self.sub_netlists.index(net) ValueError: <glayout.flow.spice.netlist.Netlist object at 0x7f38bb7e28c0> is not in list .

While using the connect_node() for the 'nfet'/'pfet' primitive, what should be the circuit_name argument to be able to use the function ?

@harshkhandeparkar : I've now updated the netlist construct using this.

harshkhandeparkar · 2024-12-12T09:23:32Z

+					with_dummy=False, #with_dummy,
+					with_substrate_tap=False,
+					**kwargs)
+	print("FETS are instantiated now")


Is this required? It might clutter the logs. Perhaps it can be changed to give out slightly more specific information.

harshkhandeparkar · 2024-12-12T09:25:48Z

+	if device in ['nmos', 'nfet']:
+		print(f"NMOS device")
+		# add a pwell 
+		top_level.add_padding(layers = (pdk.get_glayer("pwell"),), default = pdk.get_grule("pwell", "active_tap")["min_enclosure"], )


Both of these statements only change the value nwell or pwell, code duplication can be reduced.

harshkhandeparkar · 2024-12-12T09:27:11Z

+
+
+	generated_netlist_for_lvs = top_level.info['netlist'].generate_netlist()
+	print(f"Type of generated netlist is :", generated_netlist_for_lvs)


It would be good if this is done outside the function. This function returns a component, the extra code may cause unintended side effects.

harshkhandeparkar · 2024-12-12T09:28:17Z

+		print(f"Verify the file availability and type: ", generated_netlist_for_lvs, type(generated_netlist_for_lvs))
+	return top_level
+
+# Function to add labels to the port definitions


This can be moved into a docstring.

@harshkhandeparkar : Could you kindly provide a reference to the docstring function that could be used ?

harshkhandeparkar · 2024-12-12T09:29:08Z

+
+	return CMS.flatten()
+
+mapped_pdk_build = sky130


This code should also be in a separate file.

harshkhandeparkar · 2024-12-12T09:32:32Z

+	top_level = Component("cascode common source amplifier")
+	# Create the transistors
+	print(f"Creating ", device, " devices with these parameters: ",m1_fingers,m1_multipliers, m2_fingers, m2_multipliers)
+	if device in ['nmos', 'nfet']:


Code duplication can be reduced in the FET instantiation as only the type of fet changes with the rest of the code being same.

Sud-ana · 2024-12-12T16:14:39Z

Thanks harshkhandeparkar for the feedbacks. Will work on them and address the comments. Thanks.

…e netlist.

msaligane · 2025-04-10T17:16:41Z

@Sud-ana Any updates?

Sud-ana added 11 commits September 12, 2024 14:40

Added the cascode common source amplifier with interdigitated fingers.

15687d1

Added the M1 and M2 FETs to top_level component. Reference added to m…

c3fe9f8

…ove the M2 north of M1.

Added reference to the input and cascode transistor with options for …

2d20695

…horizontal or vertical placement.

Source of M2 connected to Drain of M1 with generic port definition.

92efd11

Added port prefix M1 and M2 .

f1909b3

Removed comments

d0b1504

LVS fails.

fb86c0a

LVS fail again.

ce42551

Multiple fingers and multipliers supported for the NMOS/PMOS devices.

7340dcc

Documentation function updted

d3e2f02

comment updated

f0ad2de

Sud-ana marked this pull request as draft September 23, 2024 23:15

msaligane requested a review from chetanyagoyal September 26, 2024 14:59

Sud-ana added 4 commits October 2, 2024 21:08

Adding ports

fe2ae5e

Adding ports

32e2fcd

Adding ports

c0bbccd

Updated the netlist function.

e8bb0b4

Port size reduced.

460b303

chetanyagoyal requested changes Nov 1, 2024

View reviewed changes

Port labelling added.

4fb49f9

Sud-ana changed the title ~~cascode common source block~~ Chipathon2024 Mahowald-ers Cascode Common Source Block Nov 16, 2024

Sud-ana added 3 commits November 16, 2024 10:37

Removed the XDUMMY transistor devices

ef9615b

Alternative pin placement for VIN VBIAS IIN VSS.

242bd03

Adding the labels for the ports.

bbf4ea5

Sud-ana added 3 commits November 28, 2024 10:31

Added the layer labels for the nets and pins.

139840e

GLayout has 6 nets while schematic has 5nets. Pin list matches after …

1994d1b

…LVS but netlist fails to match. Debug required.

LVS matches for layout and schematic.

2188092

Cleaning up the code.

1fdd82d

harshkhandeparkar reviewed Dec 12, 2024

View reviewed changes

Sud-ana added 4 commits February 23, 2025 12:41

Added netlist connect nodes for pfet andnfet.

202f964

Using connect netlist from pfet and nfet primitive blocks to build th…

513feb4

…e netlist.

Removed duplicates for line addition.

96090cd

Initial draft for regulated cascode common source block added.

36888cb


		instance_format = "X{name} {nodes} {circuit_name} l={length} w={width} m={mult}"

		return Netlist(



		generated_netlist_for_lvs = top_level.info['netlist'].generate_netlist()
		print(f"Type of generated netlist is :", generated_netlist_for_lvs)

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Sud-ana commented Sep 23, 2024

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chetanyagoyal commented Oct 17, 2024

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Sud-ana commented Nov 28, 2024

Net: IOUT |Net: IOUT sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1 | Net: VSS |Net: VSS sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/4 = 2 | Net: w_n386_n737# |(no matching net) sky130_fd_pr__nfet_01v8/4 = 2 |

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Sud-ana commented Dec 12, 2024

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Sud-ana commented Oct 17, 2024 •

edited

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Net: IOUT |Net: IOUT
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
|
Net: VSS |Net: VSS
sky130_fd_pr__nfet_01v8/(1|3) = 1 | sky130_fd_pr__nfet_01v8/(1|3) = 1
| sky130_fd_pr__nfet_01v8/4 = 2
|
Net: w_n386_n737# |(no matching net)
sky130_fd_pr__nfet_01v8/4 = 2 |