[SYCL] Implement host pipe unique name generation and mapping calls#8009
[SYCL] Implement host pipe unique name generation and mapping calls#8009bader merged 14 commits intointel:syclfrom
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Could you please add FE tests? |
Yep, I'll do that |
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@elizabethandrews - Now that we have [[__sycl_detail__::sycl_type(...)]], could this be accomplished using it? If so, we may consider doing the same for [[__sycl_detail__::device_global]]
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I think we can use sycl_type here. I have a JIRA to replace device_global to use sycl_type as well. Just haven't gotten around to it.
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@elizabethandrews @steffenlarsen Are there examples or documentation for sycl_type? I took a quick look in the repo and it's not clear to me how I should use it here.
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@elizabethandrews @steffenlarsen Updated. Though I know it's not best practice, I copied the static function isSyclType() from SemaSYCL.cpp to do the type check in CodeGenModule. Let me know if there's a common place where this can be put and I can make that change as well.
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We are planning on moving the CompileTimePropertiesPass to be an LLVM pass rather than a sub-feature of sycl-post-link, in which case we won't need this. See #7527. Note also this may affect the sycl-post-link related changes in this PR, but it should be resolvable.
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@steffenlarsen Now that the CompileTimePropertiesPass change was merged, I rebased, moved my host pipe change out of sycl-post-link, and removed the host-pipe arg from the driver.
Fznamznon
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I'm wondering, what is the difference between a host pipe and a device global? Can we just use a device global of a particular type to define a host pipe instead?
Device globals involve creating storage on the device that is accessible by all kernels. Host pipes can be connected to only one kernel, and do not involve creating storage but are linked to specialized hardware. The commonality is simply that they both require a mechanism to translate addresses in host space to some logical name that the backend compiler knows about. |
elizabethandrews
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Sorry for the delay in review. This PR fell off my radar. FE changes look ok to me. Just a minor comment about test
premanandrao
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(sorry for the late review. My notifications weren't quite working.)
FE changes look okay to me.
smanna12
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FE changes look OK to me
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@KseniyaTikhomirova I didn't mean to remove you from the review list, I'd only hit the "re-request" button for @steffenlarsen. I'm not sure who else needs to review this to enable merging. |
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Missing reviews from @intel/dpcpp-clang-driver-reviewers & @intel/dpcpp-tools-reviewers . |
Hello, do not worry. Steffen approval is enough on behalf of SYCL RT reviewers side😊 |
AlexeySachkov
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sycl-post-link part LGTM
Co-authored-by: Alexey Sachkov <alexey.sachkov@intel.com>
Implementation of host pipes outlined in the design document in this PR:
#5850
PR for accompanying runtime changes: #7468