Fix typos

doc/tutorials/chapter_1/01_setup_installation.md

@@ -16,7 +16,7 @@ To access the Codespaces feature on the <https://github.com/intel/rohd> reposito
 
 Please note that Codespaces are free for all users with a personal GitHub account that have either a Free or Pro plan. However, there is a monthly usage limit. To learn more about this feature, visit the official GitHub Codespaces Overview page at <https://docs.github.com/en/codespaces/overview>.
 
-> All personal GitHub.com accounts have a monthly quota of free use of GitHub Codespaces included in the Free or Pro plan. You can get started using GitHub Codespaces on your personal account without changing any settings or providing payment details. You can create and use a codespaces for any repository you can clone. You can also use a template to create codespaces that are not initially associated with a repository. If you create a codespaces from an organization-owned repository, use of the codespaces will either be charged to the organization (if the organization is configured for this), or to your personal account. Codespaces created from templates are always charged to your personal account. You can continue using GitHub Codespaces beyond your monthly included storage and compute usage by providing payment details and setting a spending limit. For more information, see "About billing for GitHub Codespaces.
+> All personal GitHub.com accounts have a monthly quota of free use of GitHub Codespaces included in the Free or Pro plan. You can get started using GitHub Codespaces on your personal account without changing any settings or providing payment details. You can create and use a codespaces for any repository you can clone. You can also use a template to create codespaces that are not initially associated with a repository. If you create a codespaces from an organization-owned repository, use of the Codespaces will either be charged to the organization (if the organization is configured for this), or to your personal account. Codespaces created from templates are always charged to your personal account. You can continue using GitHub Codespaces beyond your monthly included storage and compute usage by providing payment details and setting a spending limit. For more information, see "About billing for GitHub Codespaces.
 
 ![step 1](assets/codespaces_setup/step_1.png)
 
@@ -48,7 +48,7 @@ If you can see SystemVerilog code pop up on the terminal. Well, you have success
 
 ### Step 6: Delete the CodeSpaces (Optional)
 
-To delete the codespaces, go back to <https://github.com/intel/rohd> and click on codespaces just like step 1. But this time, you will see more options. Click on the `delete` option to delete codespaces.
+To delete the Codespaces, go back to <https://github.com/intel/rohd> and click on Codespaces just like step 1. But this time, you will see more options. Click on the `delete` option to delete Codespaces.
 
 ![step 6](assets/codespaces_setup/step_6.png)
 
@@ -248,7 +248,7 @@ If you can see SystemVerilog code pop up on the terminal. Congratulation, you ar
 
 ## Docker Container Setup
 
-There are another options which is to setup on lcoal docker environment. Firstly, you must install docker in your PC.
+There are another options which is to setup on local docker environment. Firstly, you must install docker in your PC.
 
 Pre-requisites:
 
@@ -291,5 +291,5 @@ If you can see SystemVerilog code pop up on the terminal. Congratulation, you ar
 2023 February 13
 Author: Yao Jing Quek <<yao.jing.quek@intel.com>>
 
-Copyright (C) 2021-2023 Intel Corporation
+Copyright (C) 2021-2026 Intel Corporation
 SPDX-License-Identifier: BSD-3-Clause

doc/tutorials/chapter_3/00_unit_test.md

@@ -47,7 +47,7 @@ import 'package:rohd/rohd.dart';
 import 'package:test/test.dart';
 
 void main() {
-    // your rohd implmentation here!
+    // your rohd implementation here!
 }
 ```
 

doc/tutorials/chapter_4/00_basic_generation.md

@@ -9,7 +9,7 @@
 
 In this chapter:
 
-- You learn how to create an n-bit adder by utilizing dart function and class. You will start by writting unit test and slowly implement the function of the n-bit adder.
+- You learn how to create an n-bit adder by utilizing dart function and class. You will start by writing unit test and slowly implement the function of the n-bit adder.
 
 ## What is n-bit adder?
 

doc/tutorials/chapter_5/00_basic_modules.md

@@ -49,7 +49,7 @@ In ROHD, `Module` has inputs and outputs that connects them. However, there are
     }
     ```
 
-3. Logic must be defined *before* the call to `super.build()`, which always must be called **at the end of the `build()` method** if it is overidden.
+3. Logic must be defined *before* the call to `super.build()`, which always must be called **at the end of the `build()` method** if it is overridden.
 
 The `Module` base class has an optional String argument 'name' which is an instance name.
 

doc/tutorials/chapter_6/00_combinational_logic.md

@@ -69,7 +69,7 @@ The most important part that you have to notice here is the assignment operator
 
 Alright, now we know how the operator in ROHD. we can dive into the `If...Else` in ROHD. In dart, `if...else` is used as a conditional for hardware generation, we can think of it as `if` condition A filled, then generate this pieces of hardware `else` generate that pieces of hardware. While in ROHD, `If...Else` is conditionally assignment which assign signal to a port, which we can think something like `If` Logic signal `A` is high, `Then` assign output port `B` to `A`.
 
-In today tutorial, we will review how to assign value to PORT using ROHD `If...Else` conditionals. Let start by understanding ROHD `If...Else` conditionals. There are several ways of using `If...Else` in ROHD, but the most prefferable way is using `If.block` which is more readable and clean.
+In today tutorial, we will review how to assign value to PORT using ROHD `If...Else` conditionals. Let start by understanding ROHD `If...Else` conditionals. There are several ways of using `If...Else` in ROHD, but the most preferable way is using `If.block` which is more readable and clean.
 
 *Note: `If...Else` and `Case` in ROHD is written with the first letter capitalized to differentiate from the built-in dart keywords and functionality.*
 

doc/tutorials/chapter_7/00_sequential_logic.md

@@ -281,7 +281,7 @@ expect(
 
 Well, that its for unit test in Sequential Logic. After you finish the `Simulation`, you can use `Simulator.endSimulation()` to end the Simulator and await for `Simulator.simulationEnded`.
 
-There is another method of writting unit test using which is using `Simulator.registerAction()`. But we will dive into that in the next chapter.
+There is another method of writing unit test using which is using `Simulator.registerAction()`. But we will dive into that in the next chapter.
 
 You can find the executable version of code at [shift_register.dart](shift_register.dart).
 

doc/tutorials/chapter_8/01_interface.md

@@ -79,7 +79,7 @@ class Counter extends Module {
 
 ## Counter Module Interface
 
-Let us see how we can change the `ROHD` module to `Counter` interface. First, we can create a enum `CounterDirection` that have tags of `inward`, `outward` and `misc`. You can think of this as what is the category you want to group your ports. This category can be reuse between modules. `inward` port group all inputs port, `outward` group all output ports, and `misc` group all miscellanous ports such as `clk`.
+Let us see how we can change the `ROHD` module to `Counter` interface. First, we can create a enum `CounterDirection` that have tags of `inward`, `outward` and `misc`. You can think of this as what is the category you want to group your ports. This category can be reuse between modules. `inward` port group all inputs port, `outward` group all output ports, and `misc` group all miscellaneous ports such as `clk`.
 
 Then, we can create our interface `CounterInterface` that extends from parents `Interface<TagType>`. The `TagType` is the enum that we create earlier. Let create the getters to all ports for `Counter` to allows us to send signals to the interface.
 
@@ -183,7 +183,7 @@ Future<void> main() async {
 }
 ```
 
-Thats it for the ROHD interface. By using interface, you code can be a lot cleaner and readable. Hope you enjoy the tutorials. You can find the executable version of code at [counter_interface.dart](./counter_interface.dart).
+That's it for the ROHD interface. By using interface, you code can be a lot cleaner and readable. Hope you enjoy the tutorials. You can find the executable version of code at [counter_interface.dart](./counter_interface.dart).
 
 ## Exercise
 

doc/tutorials/chapter_8/02_finite_state_machine.md

@@ -35,7 +35,7 @@ Transitions between states would be triggered by events such as button presses o
 
 ## ROHD FSM
 
-In ROHD, there are abstraction level of writting FSM. Yes, you can definitely wrote the code using Sequential and Combinational like previous chapter. But, today we want to see how we can leverage the abstraction layer provided in ROHD to quickly create the Oven FSM above.
+In ROHD, there are abstraction level of writing FSM. Yes, you can definitely write the code using Sequential and Combinational like previous chapter. But, today we want to see how we can leverage the abstraction layer provided in ROHD to quickly create the Oven FSM above.
 
 First, we want to import the ROHD package and also `counter` module. We can use the counter interface we created last session.
 
@@ -64,7 +64,7 @@ class OvenModule extends Module {
 
 In ROHD, we can use `FiniteStateMachine` API library. The `FiniteStateMachine` constructs a simple FSM, using the `clk` and `reset` signals. Also accepts the `reset` state to transition to `resetState` along with the List of _states of the FSM. Later, we will also need to create a List of `state` and send to the `FiniteStateMachine`.
 
-Let start by intitialize a variable called `_oven` that is `FiniteStateMachine` with `StateIdentifier` as  `OvenState`.
+Let's start by initializing a variable called `_oven` that is a `FiniteStateMachine` with `StateIdentifier` as  `OvenState`.
 
 Besides, we can use a simple hashmap to map over the button and LED value to integer.
 
@@ -124,7 +124,7 @@ class OvenModule extends Module {
 
 Let start creating the FSM `State`. FSM `State` represent a state named `identifier` with a definition of `events` and `actions` associated with that state.
 
-- `identifier`: Identifer or name of the state.
+- `identifier`: Identifier or name of the state.
 - `events`: A map of the possible conditions that might be true and the next state that the FSM needs to transition to in each of those cases.
 - `actions`: Actions to perform while the FSM is in this state.
 

doc/user_guide/_docs/A07-bus-ranges-and-swizzling.md

@@ -2,11 +2,11 @@
 title: "Bus ranges and swizzling"
 permalink: /docs/bus-range-swizzling/
 excerpt: "Bus ranges and swizzling"
-last_modified_at: 2022-12-06
+last_modified_at: 2026-01-09
 toc: true
 ---
 
-Multi-bit busses can be accessed by single bits and ranges or composed from multiple other signals.  Slicing, swizzling, etc. are also accessible on `LogicValue`s.
+Multi-bit buses can be accessed by single bits and ranges or composed from multiple other signals.  Slicing, swizzling, etc. are also accessible on `LogicValue`s.
 
 ```dart
 var a = Logic(width:8),

doc/user_guide/_docs/A12-non-synthesizable-signal.md

@@ -2,11 +2,11 @@
 title: "Non-synthesizable signal deposition"
 permalink: /docs/non-synthesizable-signal/
 excerpt: "Non-synthesizable signal deposition"
-last_modified_at: 2022-12-06
+last_modified_at: 2026-01-09
 toc: true
 ---
 
-For testbench code or other non-synthesizable code, you can use `put` or `inject` on any `Logic` to deposit a value on the signal.  The two functions have similar behavior, but `inject` is shorthand for calling `put` inside of `Simulator.injectAction`, which allows the deposited change to propogate within the same `Simulator` tick.  Generally, you will want to use `inject` for testbench interaction with a design if it has any sequential elements.
+For testbench code or other non-synthesizable code, you can use `put` or `inject` on any `Logic` to deposit a value on the signal.  The two functions have similar behavior, but `inject` is shorthand for calling `put` inside of `Simulator.injectAction`, which allows the deposited change to propagate within the same `Simulator` tick.  Generally, you will want to use `inject` for testbench interaction with a design if it has any sequential elements.
 
 ```dart
 var a = Logic(), b = Logic(width:4);
@@ -19,4 +19,4 @@ b.inject(0xf);
 a.inject(LogicValue.x);
 ```
 
-Note: changing a value directly with `put()` will propogate the value, but it will not trigger flip-flop edge detection or cosim interaction.
+Note: changing a value directly with `put()` will propagate the value, but it will not trigger flip-flop edge detection or cosim interaction.

doc/user_guide/_docs/A16-simulator.md

@@ -2,11 +2,11 @@
 title: "ROHD Simulator"
 permalink: /docs/simulator/
 excerpt: "ROHD Simulator"
-last_modified_at: 2022-12-06
+last_modified_at: 2026-01-09
 toc: true
 ---
 
-The ROHD simulator is a static class accessible as [`Simulator`](https://intel.github.io/rohd/rohd/Simulator-class.html) which implements a simple event-based simulator.  All `Logic`s in Dart have `glitch` events which propogate values to connected `Logic`s downstream.  In this way, ROHD propogates values across the entire graph representation of the hardware (without any `Simulator` involvement required).  The simulator has a concept of (unitless) time, and arbitrary Dart functions can be registered to occur at arbitraty times in the simulator.  Asking the simulator to run causes it to iterate through all registered timestamps and execute the functions in chronological order.  When these functions deposit signals on `Logic`s, it propogates values across the hardware.  The simulator has a number of events surrounding execution of a timestamp tick so that things like `FlipFlop`s can know when clocks and signals are glitch-free.
+The ROHD simulator is a static class accessible as [`Simulator`](https://intel.github.io/rohd/rohd/Simulator-class.html) which implements a simple event-based simulator.  All `Logic`s in Dart have `glitch` events which propagate values to connected `Logic`s downstream.  In this way, ROHD propagates values across the entire graph representation of the hardware (without any `Simulator` involvement required).  The simulator has a concept of (unitless) time, and arbitrary Dart functions can be registered to occur at arbitraty times in the simulator.  Asking the simulator to run causes it to iterate through all registered timestamps and execute the functions in chronological order.  When these functions deposit signals on `Logic`s, it propagates values across the hardware.  The simulator has a number of events surrounding execution of a timestamp tick so that things like `FlipFlop`s can know when clocks and signals are glitch-free.
 
 - To register a function at an arbitraty timestamp, use `Simulator.registerAction`
 - To set a maximum simulation time, use `Simulator.setMaxSimTime`

doc/user_guide/_get-started/02-installation.md

@@ -2,7 +2,7 @@
 title: "Setup & Install"
 permalink: /get-started/setup/
 excerpt: "Instructions for installing the theme for new and existing Jekyll based sites."
-last_modified_at: 2023-01-03
+last_modified_at: 2026-01-09
 toc: true
 ---
 
@@ -30,7 +30,7 @@ Be sure to note the minimum Dart version required for ROHD specified in pubspec.
 
 ## Package Managers for Hardware
 
-In the Dart ecosystem, you can use a package manager to define all package dependencies.  A package manager allows you to define constrainted subsets of versions of all your *direct* dependencies, and then the tool will solve for a coherent set of all (direct and indirect) dependencies required to build your project.  There's no need to manually figure out tool versions, build flags and options, environment setup, etc. because it is all guaranteed to work.  Integration of other packages (whether a tool or a hardware IP) become as simple as an `import` statment.  Compare that to SystemVerilog IP integration!
+In the Dart ecosystem, you can use a package manager to define all package dependencies.  A package manager allows you to define constrained subsets of versions of all your *direct* dependencies, and then the tool will solve for a coherent set of all (direct and indirect) dependencies required to build your project.  There's no need to manually figure out tool versions, build flags and options, environment setup, etc. because it is all guaranteed to work.  Integration of other packages (whether a tool or a hardware IP) become as simple as an `import` statement.  Compare that to SystemVerilog IP integration!
 
 Read more about package managers here: <https://en.wikipedia.org/wiki/Package_manager>
 

example/example.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2023 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // example.dart
@@ -11,7 +11,7 @@
 // allow `print` messages (disable lint):
 // ignore_for_file: avoid_print
 
-// Import necessary dart pacakges for this file.
+// Import necessary dart packages for this file.
 import 'dart:async';
 
 // Import the ROHD package.

example/logic_array.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2025 Intel Corporation
+// Copyright (C) 2025-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // logic_array.dart
@@ -12,7 +12,7 @@
 // allow `print` messages (disable lint):
 // ignore_for_file: avoid_print
 
-// Import necessary dart pacakges for this file.
+// Import necessary dart packages for this file.
 import 'dart:async';
 
 // Import the ROHD package.

lib/src/collections/traverseable_collection.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2024 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // traverseable_collection.dart
@@ -19,7 +19,7 @@ import 'dart:collection';
 ///
 /// In situations where it is necessary to iterate through and frequently access
 /// elements by index, but also check whether a certain element is contained
-/// wihin it, and there are many elements, this implementation is substantially
+/// within it, and there are many elements, this implementation is substantially
 /// faster than using either a [Set] or a [List].
 class TraverseableCollection<T> with IterableMixin<T> {
   /// The underlying [Set] that stores the data.

lib/src/exceptions/logic/put_exception.dart

@@ -1,8 +1,8 @@
-// Copyright (C) 2023 Intel Corporation
+// Copyright (C) 2023-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // put_exception.dart
-// An exception that thrown when a signal failes to `put`.
+// An exception that thrown when a signal fails to `put`.
 //
 // 2023 January 5
 // Author: Max Korbel <max.korbel@intel.com>

lib/src/exceptions/logic/unassignable_exception.dart

@@ -1,8 +1,8 @@
-// Copyright (C) 2024 Intel Corporation
+// Copyright (C) 2024-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // unassignable_exception.dart
-// An exception that thrown when a signal failes to `put`.
+// An exception that thrown when a signal fails to `put`.
 //
 // 2024 October 24
 // Author: Max Korbel <max.korbel@intel.com>

lib/src/modules/conditionals/case.dart

@@ -1,4 +1,4 @@
-// Copyright (C) 2021-2025 Intel Corporation
+// Copyright (C) 2021-2026 Intel Corporation
 // SPDX-License-Identifier: BSD-3-Clause
 //
 // case.dart
@@ -158,7 +158,7 @@ class Case extends Conditional {
     }
 
     if (!expression.value.isValid) {
-      // if expression has X or Z, then propogate X's!
+      // if expression has X or Z, then propagate X's!
       driveX(drivenSignals);
       return;
     }