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Traffic-Light-Controller
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UART-Receiver
UART-Receiver PublicUART Receiver designed in Verilog HDL with FSM-based architecture supporting 8N1 asynchronous serial communication. Includes testbench, waveform analysis, block diagram, and state machine design.
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digital-lock-fsm
digital-lock-fsm PublicDigital Lock FSM designed in Verilog HDL for password-based access control. Implements finite state machine (FSM) logic to detect a predefined input sequence and generate an unlock signal. Includes…
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mini-risc-processor
mini-risc-processor PublicA custom 16-bit RISC Processor implemented in Verilog featuring ALU, Register File, Program Counter, Control Unit, Instruction Memory, and Branch Logic with complete simulation and verification.
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