- Professor Sitao Huang
- Joseph Prince
- Hong Dong
- Kyle Van
- Brad Lacy
The goal of this project is to accelerate the calculations of HDC (Hyper-dimensional Computing) using an FPGA. We want to enable embedded systems with power consumption restraints to run ML/AI applications.
To do this, we wrote a classification algorithm, in C code, that heavily uses HDC. After that, we synthesize the code on Vitis HLS so that the code can be run on the PYNQ-Z2 board using an onboard FPGA.
Then, we write the code to run the algorithm on a Jupyter Notebook on the Pynq Z2 board. The components of this algorithm that involve HDC are run on the FPGA. All these steps have been completed and will be discussed more in the paper.
This project used data from the MNIST dataset to test the speed and accuracy of the algorithm, and we compared the time it took to test with and without the FPGA to see if this project actually sped up the calculation.
