Update repository to latest upstream branch (pyftdi 0.57.1)#1
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After the master sends the request to read from a slave and after the ACK from the slave, the _send_check_ack function ends with SDA being a HI output. During this period to when the master starts clocking in the data it wants to read, some slaves pull the SDA line low. This would short the SDA output to GND, causing it to draw its max current (16mA for the FT4232). This fix makes it so that if the next action after the ACK is a read, SDA remains as an input during this period of time.
…d shorts After the master sends the request to read from a slave and after the ACK from the slave, the _send_check_ack function ends with SDA being a HI output. During this period to when the master starts clocking in the data it wants to read, some slaves pull the SDA line low. This would short the SDA output to GND, causing it to draw its max current (16mA for the FT4232). This fix makes it so that if the next action after the ACK is a read, SDA remains as an input during this period of time.
For fake tr-state: Don't restore SDA as output after checking for ACK. Instead, make it an output right before when we want to write.
…ace for USB descriptor strings
set lines to high-z after epilog when fake-tristate is enabled Similiar to issue eblot#46, FT2232H/FT4232H never *really* relax the bus after the epilog, because they don't support tristate in hardware. This leads to blocking the bus when another master (besides the FTDI) is present. Implement fake-tristate for both SCL and SDA after the epilog to unblock the bus. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Fix confusing typo
Although Python3.7 syntax is supported, PyFtdi does not want to support end-of-life'd Python versions
Added -F option to force clock mode (needed to force enable I2C on FT…
…-relax i2c: relax the bus after epilog in fake-tristate mode
Fix start address of CRC word (16 bit) when checking the remaining space for USB descriptor strings
Fake tri-state: Move SDA=output after ACK to before I2C write to avoid momentary shorts after ACK during I2C reads
because breaking compatibility is always nice and keeps devs busy.
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
Prepare for Python v3.13
When the type isn't set in the eeprom determine it from the device version instead.
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
eeprom: Fall back to device version of type not set in eeprom
This commit fixes a bug in ftconf.py where the eeprom device was not closed before exiting. This meant the kernel driver was not re-attached causing device disconnection.
bugfix(eeprom): make sure to close eeprom eblot#394
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
Add PyPI publishing workflow
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
doc: update requirements and dependencies
Correct a small mistake in the SPI API documentation. Make the set_direction call clearer to readers by adding the parameter names to the function call, and using binary so it is clear the bits correspond to the pin position.
Avoids accidential start conditions, fixes eblot#405 As a side note, _clk_lo_data_input does generate a negative glitch on SDA (if it was high) before going high-impedance. This behavior is preferable over the alternative (glitching high before going high-impedance), since the device might already be driving low on the bus to provide an ACK and we don't want brief crowbar currents.
i2c: fix reading >116 bytes with the non-optimized read path
When adaptive clocking is enabled, the MPSSE engine gets blocked waiting for the clock feedback signal to become high. This has a lot of side effects, breaking GPIO accesses, preventing further configuration commands from executing (including both 3-phase clocking as well as disabling adaptive clocking), and confusing the pyftdi read buffer. The only way to recover seems to be purge the RX buffer, at which point the FTDI will process a "disable adaptive clocking" command. To avoid getting caught in this condition, only enable adaptive clocking at the start of an I2C transaction and disable it at the end. This helps avoid any additional USB round-trips. If an I2C-related read fails to get any data (mainly when trying to read the ACK bit), assume the bus is wedged, and apply the workaround to ensure adaptive clocking is off until the next attempted I2C transaction. Tested on an FT4232H. If the DUT is unpowered, GPIO get/set will work normally, and I2C transactions raise I2cIOError/"No answer from FTDI" (unchanged). Once the DUT becomes powered, I2C transactions immediately work correctly.
i2c: glitch high rather than low when tristating SCL+SDA
Correct mistake in SPI API documentation example
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
Prepare v0.57
Signed-off-by: Emmanuel Blot <emmanuel.blot@free.fr>
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This PR merges in all upstream changes. I have manually verified all individual changes which were in place to develop pyftdiwin 4 years ago.
Note that only high level i2c functions have been tested using an FT232H device.