cvwsoc: fixes for VGA on Genesys 2.

addins/cvwsoc/vga/axi_vga_wrap.sv

@@ -318,7 +318,7 @@ module axi_vga_wrap #(
     .reg_resp_t   ( reg_resp_t ),
     // Default: 16 and 24
     // Using BufferDepth=4 and MaxReadTxns=4 was tested at least once be good for timing requirements and not have black stripes
-    .BufferDepth  ( 4 ),
+    .BufferDepth  ( 16 ),
     .MaxReadTxns  ( 4 ) 
   ) i_axi_vga (
     .clk_i         ( aclk     ),

fpga/constraints/debug-boot-uberddr3.xdc

@@ -1,42 +1,42 @@
 
 ila_add_probe u_ila_axi -net ddr3/i_s_axi_arvalid
 ila_add_probe u_ila_axi -net ddr3/o_s_axi_arready
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_araddr -msb 29 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arid -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arlen -msb 7 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arsize -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arburst -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_araddr -msb 29 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arid -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arlen -msb 7 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arsize -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_arburst -msb 1 -lsb 0 -order lsb2msb
 # R channel
 #ila_add_probe u_ila_axi -net ddr3/i_s_axi_rvalid
 #ila_add_probe u_ila_axi -net ddr3/o_s_axi_rready
 # Check: is this one optimized?
 # ila_add_probe u_ila_axi -bus ddr3/i_s_axi_rresp -msb 1 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus BUS_cb_axi_rresp -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus BUS_cb_axi_rresp -msb 1 -lsb 0 -order lsb2msb
 # ila_add_probe u_ila_axi -net ddr3/i_s_axi_rlast
 # ila_add_probe u_ila_axi -bus ddr3/i_s_axi_rdata -msb auto -lsb 0 -order lsb2msb
 # ila_add_probe u_ila_axi -bus ddr3/i_s_axi_rid -msb 3 -lsb 0 -order lsb2msb
 # AW channel
-ila_add_probe u_ila_axi -net ddr3/i_s_axi_awvalid
-ila_add_probe u_ila_axi -net ddr3/o_s_axi_awready
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awaddr -msb 29 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net ddr3/i_s_axi_awvalid
+# ila_add_probe u_ila_axi -net ddr3/o_s_axi_awready
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awaddr -msb 29 -lsb 0 -order lsb2msb
 #ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awid -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awid -msb 3 -lsb 2 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awlen -msb 7 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awsize -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awburst -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awid -msb 3 -lsb 2 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awlen -msb 7 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awsize -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_awburst -msb 1 -lsb 0 -order lsb2msb
 
 # W channel
-ila_add_probe u_ila_axi -net ddr3/i_s_axi_wvalid
+# ila_add_probe u_ila_axi -net ddr3/i_s_axi_wvalid
 #ila_add_probe u_ila_axi -net ddr3/main_w_valid
 #ila_add_probe u_ila_axi -net ddr3/user_port_axi_0_wready
-ila_add_probe u_ila_axi -net ddr3/o_s_axi_wready
-ila_add_probe u_ila_axi -net ddr3/i_s_axi_wlast
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_wstrb -msb auto -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus ddr3/i_s_axi_wdata -msb auto -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net ddr3/o_s_axi_wready
+# ila_add_probe u_ila_axi -net ddr3/i_s_axi_wlast
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_wstrb -msb auto -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus ddr3/i_s_axi_wdata -msb auto -lsb 0 -order lsb2msb
 
 
 #ila_add_probe u_ila_axi -net ddr3/user_port_axi_0_bvalid
-ila_add_probe u_ila_axi -net ddr3/o_s_axi_bvalid
-ila_add_probe u_ila_axi -net ddr3/i_s_axi_bready
+# ila_add_probe u_ila_axi -net ddr3/o_s_axi_bvalid
+# ila_add_probe u_ila_axi -net ddr3/i_s_axi_bready
 #ila_add_probe u_ila_axi -bus ddr3/main_b_param_id  -msb 3 -lsb 0 -order lsb2msb
 #ila_add_probe u_ila_axi -bus ddr3/main_b_payload_resp  -msb 1 -lsb 0 -order lsb2msb

fpga/constraints/debug-boot.xdc

@@ -50,12 +50,12 @@ ila_add_probe u_ila_spi -net wallypipelinedsoc/core/FlushM
 # ila_add_probe u_ila_spi -bus wallypipelinedsoc/core/lsu/ReadDataM  -msb 63 -lsb 0 -order lsb2msb
 
 # SD card (SPI bus) signals
-ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCCLK
-ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCIn
-ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCCS[0]
-ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCCmd
-ila_add_probe u_ila_spi -bus wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState  -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadInc
+# ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCCLK
+# ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCIn
+# ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCCS[0]
+# ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/SDCCmd
+# ila_add_probe u_ila_spi -bus wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/CurrState  -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_spi -net wallypipelinedsoc/uncoregen.uncore/sdc.sdc/ReceiveFIFOReadInc
 
 # AHB bus signals
 #ila_add_probe u_ila_spi -bus wallypipelinedsoc/core/ebu.ebu/HTRANS -msb 1 -lsb 0 -order lsb2msb
@@ -108,56 +108,56 @@ connect_debug_port u_ila_axi/clk [get_nets BUSCLK]
 
 
 # USB
-ila_add_probe u_ila_axi -bus   usb_m_axi_awid -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus  usb_m_axi_awaddr -msb 31 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus   usb_m_axi_awlen -msb 7 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus   usb_m_axi_awsize -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus   usb_m_axi_awburst -msb 1 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_awlock
-ila_add_probe u_ila_axi -bus   usb_m_axi_awcache  -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus   usb_m_axi_awprot  -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_awvalid
-ila_add_probe u_ila_axi -net usb_m_axi_awready
-
-ila_add_probe u_ila_axi -bus  usb_m_axi_wdata  -msb auto -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus   usb_m_axi_wstrb  -msb auto -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_wlast
-ila_add_probe u_ila_axi -net usb_m_axi_wvalid
-ila_add_probe u_ila_axi -net usb_m_axi_wready
-
-ila_add_probe u_ila_axi -bus   usb_m_axi_bid  -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus   usb_m_axi_bresp  -msb 1 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_bvalid
-ila_add_probe u_ila_axi -net usb_m_axi_bready
-
-ila_add_probe u_ila_axi -bus usb_m_axi_arid  -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_araddr  -msb 31 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_arlen  -msb 7 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_arsize  -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_arburst  -msb 1 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_arlock
-ila_add_probe u_ila_axi -bus usb_m_axi_arcache  -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_arprot  -msb 2 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_arvalid
-ila_add_probe u_ila_axi -net usb_m_axi_arready
-
-ila_add_probe u_ila_axi -bus  usb_m_axi_rid  -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_rdata  -msb auto -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus usb_m_axi_rresp  -msb 1 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -net usb_m_axi_rlast
-ila_add_probe u_ila_axi -net usb_m_axi_rvalid
-ila_add_probe u_ila_axi -net usb_m_axi_rready
+# ila_add_probe u_ila_axi -bus   usb_m_axi_awid -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus  usb_m_axi_awaddr -msb 31 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus   usb_m_axi_awlen -msb 7 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus   usb_m_axi_awsize -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus   usb_m_axi_awburst -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_awlock
+# ila_add_probe u_ila_axi -bus   usb_m_axi_awcache  -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus   usb_m_axi_awprot  -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_awvalid
+# ila_add_probe u_ila_axi -net usb_m_axi_awready
+
+# ila_add_probe u_ila_axi -bus  usb_m_axi_wdata  -msb auto -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus   usb_m_axi_wstrb  -msb auto -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_wlast
+# ila_add_probe u_ila_axi -net usb_m_axi_wvalid
+# ila_add_probe u_ila_axi -net usb_m_axi_wready
+
+# ila_add_probe u_ila_axi -bus   usb_m_axi_bid  -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus   usb_m_axi_bresp  -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_bvalid
+# ila_add_probe u_ila_axi -net usb_m_axi_bready
+
+# ila_add_probe u_ila_axi -bus usb_m_axi_arid  -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_araddr  -msb 31 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_arlen  -msb 7 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_arsize  -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_arburst  -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_arlock
+# ila_add_probe u_ila_axi -bus usb_m_axi_arcache  -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_arprot  -msb 2 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_arvalid
+# ila_add_probe u_ila_axi -net usb_m_axi_arready
+
+# ila_add_probe u_ila_axi -bus  usb_m_axi_rid  -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_rdata  -msb auto -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus usb_m_axi_rresp  -msb 1 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net usb_m_axi_rlast
+# ila_add_probe u_ila_axi -net usb_m_axi_rvalid
+# ila_add_probe u_ila_axi -net usb_m_axi_rready
 
 
 # SDHCI probes
-ila_add_probe u_ila_axi -net sd_clk_o
-ila_add_probe u_ila_axi -net sd_cd_ni
-ila_add_probe u_ila_axi -net sd_cmd_en
-ila_add_probe u_ila_axi -net sd_cmd_o
-ila_add_probe u_ila_axi -net sd_cmd_i
-ila_add_probe u_ila_axi -net sd_dat_en
-ila_add_probe u_ila_axi -bus sd_dat_o -msb 3 -lsb 0 -order lsb2msb
-ila_add_probe u_ila_axi -bus sd_dat_i -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -net sd_clk_o
+# ila_add_probe u_ila_axi -net sd_cd_ni
+# ila_add_probe u_ila_axi -net sd_cmd_en
+# ila_add_probe u_ila_axi -net sd_cmd_o
+# ila_add_probe u_ila_axi -net sd_cmd_i
+# ila_add_probe u_ila_axi -net sd_dat_en
+# ila_add_probe u_ila_axi -bus sd_dat_o -msb 3 -lsb 0 -order lsb2msb
+# ila_add_probe u_ila_axi -bus sd_dat_i -msb 3 -lsb 0 -order lsb2msb
 
 # # SDHCI debug taps: command path
 # ila_add_probe u_ila_axi -bus gen_axi_sdhci.dbg_sdhci_current_cmd -msb 5 -lsb 0 -order lsb2msb
@@ -271,12 +271,12 @@ ila_add_probe u_ila_axi -net m_axi_wlast
 ila_add_probe u_ila_axi -net m_axi_bvalid
 ila_add_probe u_ila_axi -net m_axi_bready
 # #ila_add_probe u_ila_axi -bus m_axi_bresp -msb 1 -lsb 0 -order lsb2msb
-# ila_add_probe u_ila_axi -bus m_axi_araddr  -msb 31 -lsb 0 -order lsb2msb
+ila_add_probe u_ila_axi -bus m_axi_araddr  -msb 31 -lsb 0 -order lsb2msb
 # ila_add_probe u_ila_axi -bus m_axi_arlen -msb 7 -lsb 0 -order lsb2msb
 # ila_add_probe u_ila_axi -bus m_axi_arsize -msb 2 -lsb 0 -order lsb2msb
 # ila_add_probe u_ila_axi -bus m_axi_arburst -msb 1 -lsb 0 -order lsb2msb
-# ila_add_probe u_ila_axi -net m_axi_arvalid
-# ila_add_probe u_ila_axi -net m_axi_arready
+ila_add_probe u_ila_axi -net m_axi_arvalid
+ila_add_probe u_ila_axi -net m_axi_arready
 # ila_add_probe u_ila_axi -bus m_axi_rdata -msb 63 -lsb 0 -order lsb2msb
 # ila_add_probe u_ila_axi -net m_axi_rvalid
 # ila_add_probe u_ila_axi -net m_axi_rready

fpga/generator/Makefile

@@ -53,6 +53,7 @@ genesys2soc: export board := genesys2soc
 genesys2soc: export SYSTEMCLOCK := 40000000
 genesys2soc: export MAXSDCCLOCK  := 5000000
 genesys2soc: export MIG_ADDR_WIDTH  :=  30
+genesys2soc: export MEM_WIDTH  :=  64
 genesys2soc: FPGA_GENESYS2SOC
 
 genesys2socxlnx: export XILINX_PART := xc7k325tffg900-2

linux/devicetree/wally-genesys2rv32soc.dts

@@ -9,6 +9,17 @@
   chosen {
     bootargs = "root=/dev/mmcblk1p5 rw console=ttyS0,115200 loglevel=7 init=/sbin/init rootwait ";
     stdout-path = "/soc/uart@10000000";
+
+    //320 x 240
+    framebuffer0: framebuffer@BFF00000 {
+      compatible = "simple-framebuffer";
+      reg = <0x0 0xBFF00000 0x0 0x00025800>;
+      width = <320>;
+      height = <240>;
+      stride = <640>;  // 320 * 2
+      format = "r5g6b5";
+    };
+
   };
 
   memory@80000000 {
@@ -254,15 +265,4 @@
     };
   };
 
-
-  //320 x 240
-  framebuffer0: framebuffer@BFF00000 {
-    compatible = "simple-framebuffer";
-    reg = <0x0 0xBFF00000 0x0 0x00025800>;
-    width = <320>;
-    height = <240>;
-    stride = <640>;  // 320 * 2
-    format = "r5g6b5";
-  };
-
 };

linux/devicetree/wally-genesys2soc.dts

@@ -9,6 +9,17 @@
   chosen {
     bootargs = "root=/dev/mmcblk1p5 rw console=ttyS0,115200 loglevel=7 init=/sbin/init rootwait ";
     stdout-path = "/soc/uart@10000000";
+
+    //320 x 240
+    framebuffer0: framebuffer@BFF00000 {
+      compatible = "simple-framebuffer";
+      reg = <0x0 0xBFF00000 0x0 0x00025800>;
+      width = <320>;
+      height = <240>;
+      stride = <640>;  // 320 * 2
+      format = "r5g6b5";
+    };
+
   };
 
   memory@80000000 {
@@ -253,14 +264,4 @@
   };
 
 
-  //320 x 240
-  framebuffer0: framebuffer@BFF00000 {
-    compatible = "simple-framebuffer";
-    reg = <0x0 0xBFF00000 0x0 0x00025800>;
-    width = <320>;
-    height = <240>;
-    stride = <640>;  // 320 * 2
-    format = "r5g6b5";
-  };
-
 };