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Cvwsoc 32bits#8

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juanschroeder merged 18 commits into
cvwsocfrom
cvwsoc_32bits
May 29, 2026
Merged

Cvwsoc 32bits#8
juanschroeder merged 18 commits into
cvwsocfrom
cvwsoc_32bits

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This PR brings:

  • Core-V Wally bugfixes for XLEN=32 to work (including bootrom for RV32 and improvement on splitfile.sh)
  • Core-V Wally bugfixes for being able to use XLEN != AHBW
  • RV32 with AHBW=32 and RV32 with AHBW=64 FPGA build targets for the Genesys 2 board. A minimal RV32 target was also added for future tests.
  • Simulation for RV32 targets, using Yocto virt32 binaries.
  • Updates for fixed ahb-to-axi4 and sdhci submodules
  • other simulation fixes (u-boot stub, JFFS2 in mtd-ram option

Tested in verilator and QEMU for RV32 an RV64.
These fixes made it possible to simulate
the SoC with AHBW=64 AND XLEN=32.
Using romfs instead of initrd makes
rootfs mount and boot 30+ million cycles
shorter.

Ramfs will be added later.
Bugfix for bug found during romfs
integration.
U-boot stub is added for emu/simulation
targets that should not run u-boot.
The Kernel is always loaded at
0x80400000 for 32 and 64 bit targets.
- Changed peripheral wrappers to be configurable
- Added USB OHCI 32-bit generated verilog
- fixed constraints to work with flexible widths
- Reworked top file not to have hardwired index
numbers.
- Commenting hack for 32-bit case. Now readmemh
is done for both XLEN=32 and XLEN=64
- Fixes on splitfile.sh. Split depends on target
XLEN plus other params (not a hardcoded K).

Remark: 32-bit bootrom compilation is missing.
- The builds were tested for different combinations of
XLEN and AHBW.
- Clock frequency for RV32 was increased to 55 MHz. It
doesn't meet timing requirements but it seems to run ok.
- Different FPGA build targets were added. All RV32
targets should run the same OpenSBI/U-boot/Linux but
bootrom binaries need different treatment depending on
AHBW.
- Simulation assumes RV32=1 => AHBW=32, but that can
be overridden.
@juanschroeder juanschroeder merged commit d09f758 into cvwsoc May 29, 2026
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