feat: Impl translate for aarch64

Cargo.toml

@@ -29,6 +29,7 @@ thiserror = "2.0.17"
 tokio = { version = "1.49.0", features = ["full"] }
 tracing = "0.1.44"
 tracing-subscriber = { version = "0.3.22", features = ["fmt", "env-filter"] }
+vm-aarch64 = { path = "crates/vm-aarch64" }
 vm-bootloader = { path = "crates/vm-bootloader" }
 vm-core = { path = "crates/vm-core" }
 vm-device = { path = "crates/vm-device" }

crates/vm-aarch64/Cargo.toml

@@ -0,0 +1,7 @@
+[package]
+name = "vm-aarch64"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+bitflags = { workspace = true }

crates/vm-aarch64/src/lib.rs

@@ -0,0 +1,17 @@
+#![deny(warnings)]
+
+pub mod register;
+
+#[macro_export]
+macro_rules! get_field {
+    ($v:expr, $hi:expr, $lo:expr) => {
+        (($v >> $lo) & ((1u64 << ($hi - $lo + 1)) - 1))
+    };
+}
+
+#[macro_export]
+macro_rules! get_field_bit {
+    ($v:expr, $b:expr) => {
+        (($v >> $b) & 0x1) != 0
+    };
+}

crates/vm-aarch64/src/register.rs

@@ -0,0 +1,5 @@
+pub mod cnthctl_el2;
+pub mod id_aa64mmfr0_el1;
+pub mod sctlr_el1;
+pub mod tcr_el1;
+pub mod ttbr1_el1;

crates/vm-aarch64/src/register/cnthctl_el2.rs

@@ -0,0 +1,21 @@
+use bitflags::bitflags;
+
+bitflags! {
+    pub struct CnthctlEl2: u64 {
+        const EL0PCTEN = 1 << 0;
+        const EL0VCTEN = 1 << 1;
+        const EVNTEN = 1 << 2;
+        const EVNTDIR = 1 << 3;
+        const EVNTI = 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7;
+        const EL0VTEN = 1 << 8;
+        const EL0PTEN = 1 << 9;
+        const EL1PCTEN = 1 << 10;
+        const EL1PTEN = 1 << 11;
+        const ECV = 1 << 12;
+        const EL1TVT = 1 << 13;
+        const EL1TVCT = 1 << 14;
+        const EL1NVPCT = 1 << 15;
+        const EL1NVVCT = 1 << 16;
+        const EVNTIS = 1 << 17;
+    }
+}

crates/vm-aarch64/src/register/id_aa64mmfr0_el1.rs

@@ -0,0 +1,15 @@
+use crate::get_field;
+
+pub struct IdAa64mmfr0El1(pub u64);
+
+impl From<u64> for IdAa64mmfr0El1 {
+    fn from(value: u64) -> Self {
+        IdAa64mmfr0El1(value)
+    }
+}
+
+impl IdAa64mmfr0El1 {
+    pub fn pa_range(&self) -> u8 {
+        get_field!(self.0, 3, 0) as u8
+    }
+}

crates/vm-aarch64/src/register/sctlr_el1.rs

@@ -0,0 +1,62 @@
+use bitflags::bitflags;
+
+bitflags! {
+    pub struct SctlrEl1: u64 {
+        const M = 1 << 0;
+        const A = 1 << 1;
+        const C = 1 << 2;
+        const SA = 1 << 3;
+        const SA0 = 1 << 4;
+        const CP15BEN = 1 << 5;
+        const nAA = 1 << 6;
+        const ITD = 1 << 7;
+        const SED = 1 << 8;
+        const UMA = 1 << 9;
+        const EnRCTX = 1 << 10;
+        const EOS = 1 << 11;
+        const I = 1 << 12;
+        const EnDB = 1 << 13;
+        const DZE = 1 << 14;
+        const UCT = 1 << 15;
+        const nTWI = 1 << 16;
+
+        // RESERVE
+
+        const nTWE = 1 << 18;
+        const WXN = 1 << 19;
+        const TSCXT = 1 << 20;
+        const IESB = 1 << 21;
+        const EIS = 1 << 22;
+        const SPAN = 1 << 23;
+        const EOE = 1 << 24;
+        const EE = 1 << 25;
+        const UCI = 1 << 26;
+        const EnDA = 1 << 27;
+        const nTLSMD = 1 << 28;
+        const LSMAOE = 1 << 29;
+        const EnIB = 1 << 30;
+        const EnIA = 1 << 31;
+
+        // RESERVE
+
+        const BT0 = 1 << 35;
+        const BT1 = 1 << 36;
+        const ITFSB = 1 << 37;
+        const TCF0 = 1 << 38 | 1 << 39;
+        const TCF = 1 << 40 | 1 << 41;
+        const ATA0 = 1 << 42;
+        const ATA = 1 << 43;
+        const DSSBS = 1 << 44;
+        const TWEDEn = 1 << 45;
+        const TWEDEL = 1 << 46 | 1 << 47 | 1 << 48 | 1 << 49;
+
+        // RESERVE
+
+        const EnASR = 1 << 54;
+        const EnAS0 = 1 << 55;
+        const EnALS = 1 << 56;
+        const EPAN = 1 << 57;
+
+        // RESERVE
+    }
+}

crates/vm-aarch64/src/register/tcr_el1.rs

@@ -0,0 +1,28 @@
+use crate::get_field;
+use crate::get_field_bit;
+
+pub struct TcrEl1(pub u64);
+
+impl From<u64> for TcrEl1 {
+    fn from(v: u64) -> Self {
+        TcrEl1(v)
+    }
+}
+
+impl TcrEl1 {
+    pub fn ds(&self) -> bool {
+        get_field_bit!(self.0, 59)
+    }
+
+    pub fn ips(&self) -> u8 {
+        get_field!(self.0, 34, 32) as u8
+    }
+
+    pub fn tg1(&self) -> u8 {
+        get_field!(self.0, 31, 30) as u8
+    }
+
+    pub fn t1sz(&self) -> u8 {
+        get_field!(self.0, 21, 16) as u8
+    }
+}

crates/vm-aarch64/src/register/ttbr1_el1.rs

@@ -0,0 +1,15 @@
+use crate::get_field;
+
+pub struct Ttbr1El1(pub u64);
+
+impl From<u64> for Ttbr1El1 {
+    fn from(value: u64) -> Self {
+        Ttbr1El1(value)
+    }
+}
+
+impl Ttbr1El1 {
+    pub fn baddr(&self) -> u64 {
+        get_field!(self.0, 47, 0)
+    }
+}

crates/vm-core/Cargo.toml

@@ -16,8 +16,10 @@ serde_json = { workspace = true }
 thiserror = { workspace = true }
 tokio = { workspace = true }
 vm-fdt = { workspace = true }
+vm-mm = { workspace = true }
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
+vm-aarch64 = { workspace = true }
 futures = { workspace = true }
 static_assertions = { workspace = true }
 strum_macros = { workspace = true }

crates/vm-core/src/arch.rs

@@ -6,4 +6,5 @@ pub mod x86_64;
 
 pub mod irq;
 pub mod layout;
+pub mod mmu;
 pub mod registers;

crates/vm-core/src/arch/aarch64/vcpu.rs

@@ -1,8 +1,9 @@
+use vm_aarch64::register::cnthctl_el2::CnthctlEl2;
+use vm_aarch64::register::sctlr_el1::SctlrEl1;
+
 use crate::arch::aarch64::vcpu::reg::CoreRegister;
 use crate::arch::aarch64::vcpu::reg::FpRegister;
 use crate::arch::aarch64::vcpu::reg::SysRegister;
-use crate::arch::aarch64::vcpu::reg::cnthctl_el2::CnthctlEl2;
-use crate::arch::aarch64::vcpu::reg::sctlr_el1::SctlrEl1;
 use crate::arch::registers::aarch64::AArch64CoreRegisters;
 use crate::arch::registers::aarch64::AArch64Registers;
 use crate::arch::registers::aarch64::AArch64SysRegisters;
@@ -31,7 +32,7 @@ pub trait AArch64Vcpu {
 
     fn set_fp_reg(&mut self, reg: FpRegister, value: u128) -> Result<(), VcpuError>;
 
-    fn get_sys_reg(&mut self, reg: SysRegister) -> Result<u64, VcpuError>;
+    fn get_sys_reg(&self, reg: SysRegister) -> Result<u64, VcpuError>;
 
     fn set_sys_reg(&mut self, reg: SysRegister, value: u64) -> Result<(), VcpuError>;
 
@@ -86,5 +87,5 @@ pub trait AArch64Vcpu {
         Ok(())
     }
 
-    fn translate_gva_to_gpa(&self, gva: u64) -> Result<u64, VcpuError>;
+    fn translate_gva_to_gpa(&self, gva: u64) -> Result<Option<u64>, VcpuError>;
 }

crates/vm-core/src/arch/aarch64/vcpu/reg.rs

@@ -125,6 +125,9 @@ pub enum SysRegister {
     OslarEl1,
     OslsrEl1,
     OsdlrEl1,
+    TcrEl1,
+    Ttbr1El1,
+    IdAa64mmfr0El1,
 }
 
 impl SysRegister {
@@ -170,92 +173,3 @@ impl SysRegister {
 //         }
 //     }
 // }
-
-pub mod sctlr_el1 {
-    use bitflags::bitflags;
-
-    bitflags! {
-        pub struct SctlrEl1: u64 {
-            const M = 1 << 0;
-            const A = 1 << 1;
-            const C = 1 << 2;
-            const SA = 1 << 3;
-            const SA0 = 1 << 4;
-            const CP15BEN = 1 << 5;
-            const nAA = 1 << 6;
-            const ITD = 1 << 7;
-            const SED = 1 << 8;
-            const UMA = 1 << 9;
-            const EnRCTX = 1 << 10;
-            const EOS = 1 << 11;
-            const I = 1 << 12;
-            const EnDB = 1 << 13;
-            const DZE = 1 << 14;
-            const UCT = 1 << 15;
-            const nTWI = 1 << 16;
-
-            // RESERVE
-
-            const nTWE = 1 << 18;
-            const WXN = 1 << 19;
-            const TSCXT = 1 << 20;
-            const IESB = 1 << 21;
-            const EIS = 1 << 22;
-            const SPAN = 1 << 23;
-            const EOE = 1 << 24;
-            const EE = 1 << 25;
-            const UCI = 1 << 26;
-            const EnDA = 1 << 27;
-            const nTLSMD = 1 << 28;
-            const LSMAOE = 1 << 29;
-            const EnIB = 1 << 30;
-            const EnIA = 1 << 31;
-
-            // RESERVE
-
-            const BT0 = 1 << 35;
-            const BT1 = 1 << 36;
-            const ITFSB = 1 << 37;
-            const TCF0 = 1 << 38 | 1 << 39;
-            const TCF = 1 << 40 | 1 << 41;
-            const ATA0 = 1 << 42;
-            const ATA = 1 << 43;
-            const DSSBS = 1 << 44;
-            const TWEDEn = 1 << 45;
-            const TWEDEL = 1 << 46 | 1 << 47 | 1 << 48 | 1 << 49;
-
-            // RESERVE
-
-            const EnASR = 1 << 54;
-            const EnAS0 = 1 << 55;
-            const EnALS = 1 << 56;
-            const EPAN = 1 << 57;
-
-            // RESERVE
-        }
-    }
-}
-
-pub mod cnthctl_el2 {
-    use bitflags::bitflags;
-
-    bitflags! {
-        pub struct CnthctlEl2: u64 {
-            const EL0PCTEN = 1 << 0;
-            const EL0VCTEN = 1 << 1;
-            const EVNTEN = 1 << 2;
-            const EVNTDIR = 1 << 3;
-            const EVNTI = 1 << 4 | 1 << 5 | 1 << 6 | 1 << 7;
-            const EL0VTEN = 1 << 8;
-            const EL0PTEN = 1 << 9;
-            const EL1PCTEN = 1 << 10;
-            const EL1PTEN = 1 << 11;
-            const ECV = 1 << 12;
-            const EL1TVT = 1 << 13;
-            const EL1TVCT = 1 << 14;
-            const EL1NVPCT = 1 << 15;
-            const EL1NVVCT = 1 << 16;
-            const EVNTIS = 1 << 17;
-        }
-    }
-}

crates/vm-core/src/arch/mmu.rs

@@ -0,0 +1,2 @@
+#[cfg(target_arch = "aarch64")]
+pub mod aarch64;