Lab.-of-Digital-Systems-Design

106.2【電子系】ET3804301 數位系統設計實習 Lab. of Digital Systems Design

Overview

This repository contains HDL source code, simulation testbenches, and project files for a series of laboratory exercises in digital systems design using Intel (Altera) Quartus and ModelSim. Each lab/homework directory includes the Verilog modules, pin assignment files, and simulation setups required to build and verify designs on the DE2-115 FPGA board.

Repository Structure

• hw01/, hw02/, hw3/, lab4/: Project folders for each assignment/lab
  • *.v: Verilog HDL source files
  • *_tb.v: Testbench sources for simulation
  • *.qpf, *.qsf, *.qws: Quartus project files and settings
  • incremental_db/, db/, output_files/, simulation/: Tool-generated or project-specific subdirectories
• DE2_115_pin_assignments.csv: Pin map reference for the DE2-115 board
• README.md: This document

Prerequisites

• Quartus II / Intel Quartus Prime (version compatible with DE2-115 projects)
• ModelSim (Intel FPGA Edition recommended) for running simulations
• DE2-115 FPGA board (for hardware deployment)

Getting Started

Clone

git clone https://github.com/kuoyaoming/Lab.-of-Digital-Systems-Design.git
cd Lab.-of-Digital-Systems-Design

Open in Quartus

1. Launch Quartus.
2. Open the desired project by selecting the corresponding .qpf file (e.g., hw01/hw01.qpf).
3. Review or update device and pin assignments as needed (.qsf and provided CSV).

Build (Synthesis and Fitter)

1. In Quartus, set the active project to the target lab/homework.
2. Run Analysis & Synthesis.
3. Run Fitter (Place & Route).
4. Generate programming file (.sof).

Program the FPGA

1. Connect the DE2-115 board via USB-Blaster.
2. Open Programmer in Quartus.
3. Select the generated .sof file from output_files/.
4. Click "Start" to program the device.

Simulation with ModelSim

There are ready-to-use testbenches (e.g., *_tb.v). You can run simulations via Quartus-ModelSim integration or directly in ModelSim.

Run in ModelSim (CLI example)

# From the project folder (e.g., hw01/)
vsim -do simulation/modelsim/simulate.do

If a do script is not available, compile sources manually in ModelSim:

vlib work
vlog *.v
vsim -c work.hw01_tb -do "run -all; quit"

Adjust the top-level testbench target as needed (e.g., hw02_tb, lab3_tb).

Notes

• Some subfolders such as incremental_db/, db/, and output_files/ are tool-generated. They can be regenerated by Quartus and are kept here for convenience.
• PDFs named 實習題目-*.pdf contain the original lab assignments/specifications.

License

This repository is intended for educational purposes. If you plan to reuse code, please include proper attribution to the original author(s) and course.